CLKMGR Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.800s	359.547us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.410s	268.749us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.950s	127.625us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	4.410s	273.528us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.820s	560.404us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.070s	110.628us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.950s	127.625us	20	20	100.00
		clkmgr_csr_aliasing	2.820s	560.404us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.020s	127.268us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.860s	344.861us	50	50	100.00
V2	extclk	clkmgr_extclk	1.300s	178.926us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.080s	147.056us	50	50	100.00
V2	jitter	clkmgr_smoke	1.800s	359.547us	50	50	100.00
V2	frequency	clkmgr_frequency	19.160s	2.360ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	18.180s	2.420ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.160s	2.360ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.058m	9.220ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.970s	152.880us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.330s	198.806us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.030s	423.531us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.030s	423.531us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.410s	268.749us	5	5	100.00
		clkmgr_csr_rw	0.950s	127.625us	20	20	100.00
		clkmgr_csr_aliasing	2.820s	560.404us	5	5	100.00
		clkmgr_same_csr_outstanding	1.500s	62.679us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.410s	268.749us	5	5	100.00
		clkmgr_csr_rw	0.950s	127.625us	20	20	100.00
		clkmgr_csr_aliasing	2.820s	560.404us	5	5	100.00
		clkmgr_same_csr_outstanding	1.500s	62.679us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.440s	316.171us	5	5	100.00
		clkmgr_tl_intg_err	3.470s	443.157us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.590s	548.973us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.590s	548.973us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.590s	548.973us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.590s	548.973us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.030s	647.618us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.470s	443.157us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.160s	2.360ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	18.180s	2.420ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.590s	548.973us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.990s	408.469us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.370s	197.024us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.390s	203.215us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.240s	156.707us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	2.200s	487.292us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.950s	127.625us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.440s	316.171us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.950s	127.625us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.950s	127.625us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.440s	316.171us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.190s	1.304ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	24.484m	233.438ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

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