CLKMGR Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.480s	238.423us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.900s	75.657us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.120s	106.387us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.270s	537.216us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	4.030s	893.012us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.360s	198.428us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.120s	106.387us	20	20	100.00
		clkmgr_csr_aliasing	4.030s	893.012us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.130s	156.488us	50	50	100.00
V2	trans_enables	clkmgr_trans	2.200s	455.900us	50	50	100.00
V2	extclk	clkmgr_extclk	1.280s	216.106us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.870s	92.869us	50	50	100.00
V2	jitter	clkmgr_smoke	1.480s	238.423us	50	50	100.00
V2	frequency	clkmgr_frequency	16.150s	2.123ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.400s	2.424ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	16.150s	2.123ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.265m	10.729ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	1.040s	166.984us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.090s	128.015us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.230s	514.226us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.230s	514.226us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.900s	75.657us	5	5	100.00
		clkmgr_csr_rw	1.120s	106.387us	20	20	100.00
		clkmgr_csr_aliasing	4.030s	893.012us	5	5	100.00
		clkmgr_same_csr_outstanding	2.940s	745.280us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.900s	75.657us	5	5	100.00
		clkmgr_csr_rw	1.120s	106.387us	20	20	100.00
		clkmgr_csr_aliasing	4.030s	893.012us	5	5	100.00
		clkmgr_same_csr_outstanding	2.940s	745.280us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.190s	391.466us	5	5	100.00
		clkmgr_tl_intg_err	6.720s	1.836ms	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.880s	974.516us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.880s	974.516us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.880s	974.516us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.880s	974.516us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.500s	431.526us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	6.720s	1.836ms	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	16.150s	2.123ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.400s	2.424ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.880s	974.516us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.560s	578.599us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.160s	152.656us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.100s	156.830us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.450s	221.650us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.330s	167.139us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.120s	106.387us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.190s	391.466us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.120s	106.387us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.120s	106.387us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.190s	391.466us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.390s	1.286ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	21.945m	178.272ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.79	100.00	100.00	98.81	97.01	98.80

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