CLKMGR Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.450s	250.753us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.060s	102.101us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.070s	103.164us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.700s	1.331ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.180s	212.003us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.010s	111.135us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.070s	103.164us	20	20	100.00
		clkmgr_csr_aliasing	2.180s	212.003us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.060s	139.555us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.390s	183.159us	50	50	100.00
V2	extclk	clkmgr_extclk	1.390s	211.808us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.960s	140.476us	50	50	100.00
V2	jitter	clkmgr_smoke	1.450s	250.753us	50	50	100.00
V2	frequency	clkmgr_frequency	17.310s	2.361ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.770s	2.296ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.310s	2.361ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.288m	11.117ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.930s	77.053us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.330s	226.794us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.450s	491.079us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.450s	491.079us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.060s	102.101us	5	5	100.00
		clkmgr_csr_rw	1.070s	103.164us	20	20	100.00
		clkmgr_csr_aliasing	2.180s	212.003us	5	5	100.00
		clkmgr_same_csr_outstanding	2.440s	473.070us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.060s	102.101us	5	5	100.00
		clkmgr_csr_rw	1.070s	103.164us	20	20	100.00
		clkmgr_csr_aliasing	2.180s	212.003us	5	5	100.00
		clkmgr_same_csr_outstanding	2.440s	473.070us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.290s	331.908us	5	5	100.00
		clkmgr_tl_intg_err	4.540s	983.452us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.540s	779.480us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.540s	779.480us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.540s	779.480us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.540s	779.480us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	8.190s	2.339ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.540s	983.452us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.310s	2.361ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.770s	2.296ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.540s	779.480us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.560s	275.718us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.850s	400.783us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.120s	91.057us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.170s	123.257us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.380s	191.319us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.070s	103.164us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.290s	331.908us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.070s	103.164us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.070s	103.164us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.290s	331.908us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.820s	2.627ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	56.468m	1.002s	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

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