CLKMGR Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.620s 321.899us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.870s 23.235us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.070s 117.849us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 15.130s 4.725ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 3.380s 702.580us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.440s 497.385us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.070s 117.849us 20 20 100.00
clkmgr_csr_aliasing 3.380s 702.580us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.960s 101.257us 50 50 100.00
V2 trans_enables clkmgr_trans 1.910s 406.791us 50 50 100.00
V2 extclk clkmgr_extclk 1.520s 256.423us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.100s 158.873us 50 50 100.00
V2 jitter clkmgr_smoke 1.620s 321.899us 50 50 100.00
V2 frequency clkmgr_frequency 17.720s 2.362ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.070s 2.294ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.720s 2.362ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.700m 14.576ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.890s 81.405us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.150s 110.476us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.370s 702.648us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.370s 702.648us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.870s 23.235us 5 5 100.00
clkmgr_csr_rw 1.070s 117.849us 20 20 100.00
clkmgr_csr_aliasing 3.380s 702.580us 5 5 100.00
clkmgr_same_csr_outstanding 2.590s 539.179us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.870s 23.235us 5 5 100.00
clkmgr_csr_rw 1.070s 117.849us 20 20 100.00
clkmgr_csr_aliasing 3.380s 702.580us 5 5 100.00
clkmgr_same_csr_outstanding 2.590s 539.179us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 18.540s 4.860ms 5 5 100.00
clkmgr_tl_intg_err 3.860s 818.162us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 4.150s 1.105ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 4.150s 1.105ms 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 4.150s 1.105ms 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 4.150s 1.105ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.390s 571.234us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.860s 818.162us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.720s 2.362ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.070s 2.294ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 4.150s 1.105ms 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.820s 347.908us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.870s 365.387us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.400s 249.362us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.590s 291.311us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.220s 104.890us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.070s 117.849us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 18.540s 4.860ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.070s 117.849us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.070s 117.849us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 18.540s 4.860ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.650s 1.341ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 35.049m 531.241ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results