CLKMGR Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.730s 363.874us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.920s 67.964us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.210s 170.969us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.180s 1.333ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.890s 550.293us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.870s 118.600us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.210s 170.969us 20 20 100.00
clkmgr_csr_aliasing 2.890s 550.293us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.130s 176.814us 50 50 100.00
V2 trans_enables clkmgr_trans 1.800s 330.965us 50 50 100.00
V2 extclk clkmgr_extclk 1.920s 388.107us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.950s 119.025us 50 50 100.00
V2 jitter clkmgr_smoke 1.730s 363.874us 50 50 100.00
V2 frequency clkmgr_frequency 17.730s 2.356ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.010s 2.055ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.730s 2.356ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.748m 14.656ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.990s 167.837us 50 50 100.00
V2 alert_test clkmgr_alert_test 0.950s 53.484us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.820s 1.201ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.820s 1.201ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.920s 67.964us 5 5 100.00
clkmgr_csr_rw 1.210s 170.969us 20 20 100.00
clkmgr_csr_aliasing 2.890s 550.293us 5 5 100.00
clkmgr_same_csr_outstanding 1.690s 255.090us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.920s 67.964us 5 5 100.00
clkmgr_csr_rw 1.210s 170.969us 20 20 100.00
clkmgr_csr_aliasing 2.890s 550.293us 5 5 100.00
clkmgr_same_csr_outstanding 1.690s 255.090us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.270s 1.131ms 5 5 100.00
clkmgr_tl_intg_err 6.180s 1.865ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.170s 510.179us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.170s 510.179us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.170s 510.179us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.170s 510.179us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.670s 740.872us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 6.180s 1.865ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.730s 2.356ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.010s 2.055ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.170s 510.179us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.670s 311.571us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.630s 301.062us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.270s 169.770us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.880s 381.076us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.130s 112.638us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.210s 170.969us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.270s 1.131ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.210s 170.969us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.210s 170.969us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.270s 1.131ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.620s 2.576ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 32.638m 527.131ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results