CLKMGR Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.710s	318.461us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.980s	84.731us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.150s	163.063us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	18.300s	4.779ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.620s	419.322us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.070s	68.659us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.150s	163.063us	20	20	100.00
		clkmgr_csr_aliasing	2.620s	419.322us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.070s	143.813us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.730s	329.761us	50	50	100.00
V2	extclk	clkmgr_extclk	1.450s	193.320us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.020s	152.060us	50	50	100.00
V2	jitter	clkmgr_smoke	1.710s	318.461us	50	50	100.00
V2	frequency	clkmgr_frequency	18.200s	2.479ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.740s	2.300ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	18.200s	2.479ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.410m	12.170ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.940s	123.588us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.170s	134.797us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.740s	699.629us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.740s	699.629us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.980s	84.731us	5	5	100.00
		clkmgr_csr_rw	1.150s	163.063us	20	20	100.00
		clkmgr_csr_aliasing	2.620s	419.322us	5	5	100.00
		clkmgr_same_csr_outstanding	2.630s	538.791us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.980s	84.731us	5	5	100.00
		clkmgr_csr_rw	1.150s	163.063us	20	20	100.00
		clkmgr_csr_aliasing	2.620s	419.322us	5	5	100.00
		clkmgr_same_csr_outstanding	2.630s	538.791us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.940s	749.273us	5	5	100.00
		clkmgr_tl_intg_err	3.490s	567.891us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.980s	902.969us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.980s	902.969us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.980s	902.969us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.980s	902.969us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.250s	1.189ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.490s	567.891us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	18.200s	2.479ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.740s	2.300ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.980s	902.969us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.910s	330.862us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.380s	212.451us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.750s	332.712us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.540s	248.071us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	2.110s	433.249us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.150s	163.063us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.940s	749.273us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.150s	163.063us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.150s	163.063us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.940s	749.273us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.660s	1.290ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	38.883m	595.978ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.88	100.00	100.00	98.81	97.01	98.80

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