CLKMGR Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: 1fbe1ece8d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.290s 165.119us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.860s 23.562us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.980s 86.211us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.080s 399.970us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.390s 350.396us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.860s 106.652us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.980s 86.211us 20 20 100.00
clkmgr_csr_aliasing 2.390s 350.396us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.950s 102.092us 50 50 100.00
V2 trans_enables clkmgr_trans 1.300s 113.199us 50 50 100.00
V2 extclk clkmgr_extclk 1.570s 263.357us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.980s 126.402us 50 50 100.00
V2 jitter clkmgr_smoke 1.290s 165.119us 50 50 100.00
V2 frequency clkmgr_frequency 18.990s 2.482ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.870s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.990s 2.482ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.064m 8.375ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.880s 109.968us 50 50 100.00
V2 alert_test clkmgr_alert_test 0.910s 35.787us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.490s 1.030ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.490s 1.030ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.860s 23.562us 5 5 100.00
clkmgr_csr_rw 0.980s 86.211us 20 20 100.00
clkmgr_csr_aliasing 2.390s 350.396us 5 5 100.00
clkmgr_same_csr_outstanding 2.210s 409.652us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.860s 23.562us 5 5 100.00
clkmgr_csr_rw 0.980s 86.211us 20 20 100.00
clkmgr_csr_aliasing 2.390s 350.396us 5 5 100.00
clkmgr_same_csr_outstanding 2.210s 409.652us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 6.000s 1.409ms 5 5 100.00
clkmgr_tl_intg_err 3.720s 665.653us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.570s 607.025us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.570s 607.025us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.570s 607.025us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.570s 607.025us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.710s 554.415us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.720s 665.653us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.990s 2.482ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.870s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.570s 607.025us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.710s 296.108us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.810s 306.825us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.100s 87.649us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.450s 266.223us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.300s 199.247us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.980s 86.211us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.000s 1.409ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.980s 86.211us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.980s 86.211us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.000s 1.409ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.320s 2.237ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 30.162m 499.769ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results