CLKMGR Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.460s	237.471us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.910s	43.692us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.930s	51.650us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	10.520s	2.100ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.990s	197.939us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.230s	355.148us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.930s	51.650us	20	20	100.00
		clkmgr_csr_aliasing	1.990s	197.939us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.200s	187.934us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.390s	158.845us	50	50	100.00
V2	extclk	clkmgr_extclk	1.830s	347.827us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.970s	125.884us	50	50	100.00
V2	jitter	clkmgr_smoke	1.460s	237.471us	50	50	100.00
V2	frequency	clkmgr_frequency	16.880s	2.244ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.240s	2.414ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	16.880s	2.244ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.695m	13.842ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.870s	92.605us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.060s	137.675us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.660s	526.459us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.660s	526.459us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.910s	43.692us	5	5	100.00
		clkmgr_csr_rw	0.930s	51.650us	20	20	100.00
		clkmgr_csr_aliasing	1.990s	197.939us	5	5	100.00
		clkmgr_same_csr_outstanding	3.160s	862.864us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.910s	43.692us	5	5	100.00
		clkmgr_csr_rw	0.930s	51.650us	20	20	100.00
		clkmgr_csr_aliasing	1.990s	197.939us	5	5	100.00
		clkmgr_same_csr_outstanding	3.160s	862.864us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.490s	834.710us	5	5	100.00
		clkmgr_tl_intg_err	3.900s	469.711us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	3.710s	927.547us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	3.710s	927.547us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	3.710s	927.547us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	3.710s	927.547us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.360s	614.641us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.900s	469.711us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	16.880s	2.244ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.240s	2.414ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	3.710s	927.547us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.470s	200.975us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.810s	347.744us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.470s	253.027us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.710s	348.769us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.500s	222.239us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.930s	51.650us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.490s	834.710us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.930s	51.650us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.930s	51.650us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.490s	834.710us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	5.870s	1.036ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	54.265m	1.005s	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

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