e3fb01b5e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 7.000s | 370.870us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 51.308us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 5.000s | 37.464us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 29.000s | 2.805ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 5.000s | 79.389us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 5.000s | 31.095us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 5.000s | 37.464us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 5.000s | 79.389us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| V2 | alerts | csrng_alert | 8.000s | 333.669us | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 |
| V2 | cmds | csrng_cmds | 1.667m | 9.198ms | 50 | 50 | 100.00 |
| V2 | life cycle | csrng_cmds | 1.667m | 9.198ms | 50 | 50 | 100.00 |
| V2 | stress_all | csrng_stress_all | 2.517m | 12.801ms | 46 | 50 | 92.00 |
| V2 | intr_test | csrng_intr_test | 5.000s | 125.347us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 4.000s | 18.507us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 14.000s | 802.867us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 14.000s | 802.867us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 51.308us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 37.464us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 5.000s | 79.389us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 37.534us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 51.308us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 37.464us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 5.000s | 79.389us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 37.534us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1422 | 1440 | 98.75 | |||
| V2S | tl_intg_err | csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 16.000s | 873.678us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 4.000s | 39.860us | 50 | 50 | 100.00 |
| csrng_csr_rw | 5.000s | 37.464us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 8.000s | 333.669us | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 2.517m | 12.801ms | 46 | 50 | 92.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 8.000s | 333.669us | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 2.517m | 12.801ms | 46 | 50 | 92.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 8.000s | 333.669us | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 16.000s | 873.678us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| csrng_sec_cm | 6.000s | 216.537us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 6.000s | 371.932us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 22.425us | 486 | 500 | 97.20 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 44.133m | 28.182ms | 4 | 50 | 8.00 |
| V3 | TOTAL | 4 | 50 | 8.00 | |||
| TOTAL | 1606 | 1670 | 96.17 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 7 | 77.78 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 92.83 | 93.35 | 84.31 | 95.41 | 86.43 | 92.29 | 100.00 | 97.50 | 95.17 |
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 25 failures:
0.csrng_stress_all_with_rand_reset.40909127
Line 274, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 22608293400 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xa5343b94) == 0x6
UVM_INFO @ 22608293400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.csrng_stress_all_with_rand_reset.2387990836
Line 276, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12698691126 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x1e7db494) == 0x6
UVM_INFO @ 12698691126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 15 failures:
1.csrng_stress_all_with_rand_reset.1844968666
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 22049059997 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xc61cf614) == 0x6
UVM_INFO @ 22049059997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.csrng_stress_all_with_rand_reset.290375451
Line 277, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10099951779 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x88301214) == 0x6
UVM_INFO @ 10099951779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 7 failures:
53.csrng_err.3102982466
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/53.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2042706 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2042706 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2042706 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 2042706 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 2042706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
301.csrng_err.4166624986
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/301.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 12198372 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 12198372 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 12198372 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 12198372 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 12198372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 5 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:
112.csrng_err.1185596947
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/112.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 30809649 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 30809649 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 30809649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
295.csrng_err.4176780918
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/295.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 2526845 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2526845 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2526845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 4 failures:
32.csrng_stress_all_with_rand_reset.90212444
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 31296098 PS + 13
Verilog Stack Trace:
34.csrng_stress_all_with_rand_reset.2926967387
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 5391111 PS + 14
Verilog Stack Trace:
... and 2 more failures.
UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
6.csrng_stress_all.2553786252
Line 256, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log
UVM_ERROR @ 52033957 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 52033957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.csrng_stress_all.914274745
Line 261, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all/latest/run.log
UVM_ERROR @ 482162014 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 482162014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
20.csrng_stress_all.3483510616
Line 257, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all/latest/run.log
UVM_ERROR @ 1386137811 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1386137811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.csrng_stress_all.2203555106
Line 281, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_stress_all/latest/run.log
UVM_ERROR @ 2694078156 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 2694078156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 1 failures:
23.csrng_stress_all_with_rand_reset.1403877992
Line 459, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14647723294 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
UVM_INFO @ 14647723294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 1 failures:
44.csrng_stress_all_with_rand_reset.2065494235
Line 637, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/44.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 28182437923 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
UVM_INFO @ 28182437923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
51.csrng_err.2487437202
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/51.csrng_err/latest/run.log
UVM_ERROR @ 2819044 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
UVM_INFO @ 2819044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:
282.csrng_err.1370147472
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/282.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 282.csrng_err.1370147472
coverage files:
model(design data) : /workspace/coverage/default/282.csrng_err.1370147472/icc_2fd05324_376d948a.ucm
data : /workspace/coverage/default/282.csrng_err.1370147472/icc_2fd05324_376d948a.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 22, 2023 at 00:57:33 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1