CSRNG Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 0 50 0.00
V1 csr_hw_reset csrng_csr_hw_reset 4.000s 164.586us 5 5 100.00
V1 csr_rw csrng_csr_rw 4.000s 118.167us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 18.000s 1.427ms 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 5.000s 149.536us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 5.000s 47.477us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 4.000s 118.167us 20 20 100.00
csrng_csr_aliasing 5.000s 149.536us 5 5 100.00
V1 TOTAL 55 105 52.38
V2 interrupts csrng_intr 0 200 0.00
V2 alerts csrng_alert 0 500 0.00
V2 err csrng_err 0 500 0.00
V2 cmds csrng_cmds 0 50 0.00
V2 life cycle csrng_cmds 0 50 0.00
V2 stress_all csrng_stress_all 0 50 0.00
V2 intr_test csrng_intr_test 4.000s 128.505us 50 50 100.00
V2 alert_test csrng_alert_test 0 50 0.00
V2 tl_d_oob_addr_access csrng_tl_errors 16.000s 646.608us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 16.000s 646.608us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 4.000s 164.586us 5 5 100.00
csrng_csr_rw 4.000s 118.167us 20 20 100.00
csrng_csr_aliasing 5.000s 149.536us 5 5 100.00
csrng_same_csr_outstanding 8.000s 460.180us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 4.000s 164.586us 5 5 100.00
csrng_csr_rw 4.000s 118.167us 20 20 100.00
csrng_csr_aliasing 5.000s 149.536us 5 5 100.00
csrng_same_csr_outstanding 8.000s 460.180us 20 20 100.00
V2 TOTAL 90 1440 6.25
V2S tl_intg_err csrng_sec_cm 0 5 0.00
csrng_tl_intg_err 12.000s 398.575us 20 20 100.00
V2S sec_cm_config_regwen csrng_regwen 0 50 0.00
csrng_csr_rw 4.000s 118.167us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 0 500 0.00
V2S sec_cm_intersig_mubi csrng_stress_all 0 50 0.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_update_fsm_sparse csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_ctrl_mubi csrng_alert 0 500 0.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 0 200 0.00
csrng_err 0 500 0.00
V2S sec_cm_constants_lc_gated csrng_stress_all 0 50 0.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 0 500 0.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 12.000s 398.575us 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 0 200 0.00
csrng_err 0 500 0.00
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 0 200 0.00
csrng_err 0 500 0.00
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 0 200 0.00
csrng_err 0 500 0.00
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 0 200 0.00
csrng_err 0 500 0.00
csrng_sec_cm 0 5 0.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 0 200 0.00
csrng_err 0 500 0.00
V2S TOTAL 20 75 26.67
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 165 1670 9.88

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 9 9 3 33.33
V2S 3 3 1 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
71.96 91.48 82.03 96.08 98.88 34.39 -- 100.00 23.60

Failure Buckets

Past Results