CSRNG Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	18.506us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	191.173us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	85.706us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	9.000s	142.758us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	198.294us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	118.571us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	85.706us	20	20	100.00
		csrng_csr_aliasing	6.000s	198.294us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	246.189us	200	200	100.00
V2	alerts	csrng_alert	8.000s	579.889us	500	500	100.00
V2	err	csrng_err	5.000s	22.122us	491	500	98.20
V2	cmds	csrng_cmds	8.550m	44.410ms	50	50	100.00
V2	life cycle	csrng_cmds	8.550m	44.410ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.967m	18.446ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	101.103us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	145.308us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	155.182us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	155.182us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	191.173us	5	5	100.00
		csrng_csr_rw	4.000s	85.706us	20	20	100.00
		csrng_csr_aliasing	6.000s	198.294us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	60.899us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	191.173us	5	5	100.00
		csrng_csr_rw	4.000s	85.706us	20	20	100.00
		csrng_csr_aliasing	6.000s	198.294us	5	5	100.00
		csrng_same_csr_outstanding	5.000s	60.899us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	4.000s	37.424us	5	5	100.00
		csrng_tl_intg_err	10.000s	182.013us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	63.277us	50	50	100.00
		csrng_csr_rw	4.000s	85.706us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	579.889us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.967m	18.446ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	579.889us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.967m	18.446ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	579.889us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	10.000s	182.013us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
		csrng_sec_cm	4.000s	37.424us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	246.189us	200	200	100.00
		csrng_err	5.000s	22.122us	491	500	98.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.857h	342.607ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1646	1670	98.56

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.73	93.20	84.21	95.34	86.30	92.29	100.00	97.50	95.29

Failure Buckets

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 8.csrng_stress_all_with_rand_reset.62226667168486614629807282096924082883856686564993991857665114549894098028868
    Line 635, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 53514062270 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 53514062270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.csrng_stress_all_with_rand_reset.70890874242765883788113829702653977130524654125611019823565300715994257259262
    Line 464, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 83415094043 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 83415094043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 15.csrng_stress_all_with_rand_reset.65772210953858767755495004669892357055993976838910195425015721909476650818275
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9939049949 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 9939049949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.csrng_stress_all_with_rand_reset.22536412661388709686175647838069851067463293024107396931197640351729897847291
    Line 869, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 482443315550 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 482443315550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

18.csrng_err.48315726612247870969690775924482729007843271125536433378489540202293966526819
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 16233826 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  16233826 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  16233826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

126.csrng_err.34531556901835408725824035776459189061509798763318956418923753241991288070525
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/126.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 13183046 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  13183046 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  13183046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 0.csrng_stress_all_with_rand_reset.21238034850922562347732150772122098989384314049679872133238047239051341186003
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:8433a99b-6604-4ba6-9c39-d43e6141fd11
```
  - 33.csrng_stress_all_with_rand_reset.99727117665762620193434751683970780721911006371246368133610342978097435421162
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/33.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bbad362d-71be-4c0d-a838-ac031fcbb5f0
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

55.csrng_err.41455155819860709492714823157906480518971321148624529389061545197736123811500
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/55.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 12269762 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 12269762 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 12269762 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  12269762 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  12269762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

216.csrng_err.91128176577497069715765467323419078668358220554333578877567803746782678422559
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/216.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1574810 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1574810 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1574810 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1574810 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1574810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 9.csrng_stress_all.1138107017612756509705862600381466930152640882416468995262052707077647619081
    Line 309, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 6868506883 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 6868506883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 39.csrng_stress_all.13936774366880779777993396033048643202474129285185210759195957591128683891192
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3125736754 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3125736754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

361.csrng_err.61969935419525121384658962039208311887907373866943281790705797260915694407794
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/361.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  361.csrng_err.4134047858
  
  coverage files:
    model(design data) :  /workspace/coverage/default/361.csrng_err.4134047858/icc_045766fd_29c39fee.ucm
    data               :  /workspace/coverage/default/361.csrng_err.4134047858/icc_045766fd_29c39fee.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jan 17, 2024 at 16:02:31 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1