CSRNG Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	51.740us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	7.000s	28.711us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	118.350us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	28.000s	1.346ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	21.792us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	147.073us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	118.350us	20	20	100.00
		csrng_csr_aliasing	8.000s	21.792us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	8.000s	117.321us	199	200	99.50
V2	alerts	csrng_alert	8.000s	427.488us	500	500	100.00
V2	err	csrng_err	5.000s	19.681us	488	500	97.60
V2	cmds	csrng_cmds	18.850m	118.773ms	50	50	100.00
V2	life cycle	csrng_cmds	18.850m	118.773ms	50	50	100.00
V2	stress_all	csrng_stress_all	18.383m	80.258ms	47	50	94.00
V2	intr_test	csrng_intr_test	7.000s	19.807us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	27.655us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	90.113us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	90.113us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	7.000s	28.711us	5	5	100.00
		csrng_csr_rw	7.000s	118.350us	20	20	100.00
		csrng_csr_aliasing	8.000s	21.792us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	562.004us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	7.000s	28.711us	5	5	100.00
		csrng_csr_rw	7.000s	118.350us	20	20	100.00
		csrng_csr_aliasing	8.000s	21.792us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	562.004us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	9.000s	808.928us	5	5	100.00
		csrng_tl_intg_err	13.000s	190.303us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	18.186us	50	50	100.00
		csrng_csr_rw	7.000s	118.350us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	427.488us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	18.383m	80.258ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	427.488us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	18.383m	80.258ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	427.488us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	190.303us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
		csrng_sec_cm	9.000s	808.928us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	8.000s	117.321us	199	200	99.50
		csrng_err	5.000s	19.681us	488	500	97.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.876h	246.279ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1643	1670	98.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.71	93.20	84.21	95.32	86.34	92.29	100.00	97.50	94.96

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

94.csrng_err.94561667447257319296185899938749429629630772576921794170541715172667608281032
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/94.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3687547 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3687547 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3687547 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3687547 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3687547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

101.csrng_err.22988783393513948548308966911322941552214504668722431011036927962380178257211
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/101.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1876886 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1876886 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1876886 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1876886 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1876886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 0.csrng_stress_all_with_rand_reset.44530521808557291034992702961886290127212337142329001752589344525657250103331
    Line 630, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 141171687480 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 141171687480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.9551424495032400367502190973947430884897147125680692027368300507891454046532
    Line 691, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 220134254103 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 220134254103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 5 failures:

Test csrng_err has 5 failures.

90.csrng_err.49556174164844076991882504973833555780571908127112963334275350227601415383973
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/90.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 2543075 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2543075 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2543075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

153.csrng_err.19139730744918600991711991623049925056108237264219945527174008273856109135098
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/153.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3066263 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3066263 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3066263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 8.csrng_stress_all_with_rand_reset.73626256612496056777530608782243624675937592505189350263408367156113245313173
    Line 663, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 90295393598 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 90295393598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.csrng_stress_all_with_rand_reset.59624194525747016216106673662967928454004198829700241226089243738210728646335
    Line 414, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14171453056 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 14171453056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 15.csrng_stress_all.109745775862678262946250506888019967872064431684941441848586709448151396917894
    Line 303, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  56084092 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  56084092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.csrng_stress_all.51070236807550298582512495505324396976376640899310403926098596028423534009122
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 12231411987 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 12231411987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 26.csrng_stress_all_with_rand_reset.71302754963016274285941935271729363519610315466336694939007254065046761521268
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:99afa46c-8148-465d-a7e0-76adbb22a27a
```
  - 42.csrng_stress_all_with_rand_reset.46345891070384914535049710081507435780514139815642348457670069681095861803313
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:56def35c-e551-464b-8b3e-27452345e490
```
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 18.csrng_stress_all_with_rand_reset.39701992170824958873010610585125396783646554329010380119265142791440921813397
    Line 360, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 22493378274 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @ 22493378274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job csrng-sim-xcelium_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test csrng_intr has 1 failures.
  - 26.csrng_intr.113002399444721562929990134221233287153922182923730351095086074791514947631692
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_intr/latest/run.log
```
  Job ID: smart:6b165b39-fa3f-4f7c-87ad-bb5750560aee
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

295.csrng_err.48964893371474634510865947148157977494895269096312366653111970465810584152811
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/295.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  295.csrng_err.3003362027
  
  coverage files:
    model(design data) :  /workspace/coverage/default/295.csrng_err.3003362027/icc_045766fd_29c39fee.ucm
    data               :  /workspace/coverage/default/295.csrng_err.3003362027/icc_045766fd_29c39fee.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jan 21, 2024 at 20:52:36 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1