CSRNG Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	49.236us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	44.977us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	20.499us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	25.000s	1.412ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	44.603us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	142.935us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	20.499us	20	20	100.00
		csrng_csr_aliasing	6.000s	44.603us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	40.981us	200	200	100.00
V2	alerts	csrng_alert	11.000s	198.121us	500	500	100.00
V2	err	csrng_err	8.000s	49.059us	489	500	97.80
V2	cmds	csrng_cmds	13.967m	61.443ms	50	50	100.00
V2	life cycle	csrng_cmds	13.967m	61.443ms	50	50	100.00
V2	stress_all	csrng_stress_all	17.500m	42.005ms	48	50	96.00
V2	intr_test	csrng_intr_test	10.000s	152.151us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	68.630us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	583.252us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	583.252us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	44.977us	5	5	100.00
		csrng_csr_rw	7.000s	20.499us	20	20	100.00
		csrng_csr_aliasing	6.000s	44.603us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	43.982us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	44.977us	5	5	100.00
		csrng_csr_rw	7.000s	20.499us	20	20	100.00
		csrng_csr_aliasing	6.000s	44.603us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	43.982us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	11.000s	1.202ms	5	5	100.00
		csrng_tl_intg_err	9.000s	647.582us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	24.655us	50	50	100.00
		csrng_csr_rw	7.000s	20.499us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	11.000s	198.121us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	17.500m	42.005ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	11.000s	198.121us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	17.500m	42.005ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	11.000s	198.121us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	647.582us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
		csrng_sec_cm	11.000s	1.202ms	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	40.981us	200	200	100.00
		csrng_err	8.000s	49.059us	489	500	97.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.914h	400.678ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1641	1670	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.64	93.15	84.08	95.27	86.26	92.23	100.00	97.00	95.07

Failure Buckets

UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.102095459666399129468352267210570364680522748491743908599071513987369201636400
    Line 355, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 59675784925 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 59675784925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.csrng_stress_all_with_rand_reset.88810243316390875961797699616423807947432941152862687138280798398227309455141
    Line 296, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1381035721 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 1381035721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

53.csrng_err.113486571848543310287513982426435989786321378667005347809878011178459595373032
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/53.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3689427 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3689427 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3689427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

156.csrng_err.42909689466438417246346943325527147380927521232914009453685442030957438034725
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/156.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 7769851 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7769851 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7769851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 5.csrng_stress_all_with_rand_reset.28604447335212134354043600047864873772770633327831582039375682574630827894249
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:74f1b25c-a105-49c6-a483-01cac8fbe713
```
  - 16.csrng_stress_all_with_rand_reset.97245647543028223557951997289684466526080513400852101417802201169883334160486
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/16.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:97a6e23b-eb52-430b-9e34-6a997d6ccd1d
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:636) scoreboard [scoreboard] Invalid csrng_acmd: * has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 28.csrng_stress_all_with_rand_reset.15037059370697619100774036708685723151409576142072943967387935593852544886728
    Line 384, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 29434425576 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 29434425576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.csrng_stress_all_with_rand_reset.39151085149144596194046685885909839917417993518289303304265337615525207543890
    Line 968, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 65137172920 ps: (csrng_scoreboard.sv:636) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
  UVM_INFO @ 65137172920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

71.csrng_err.26516794380237142361878869379171146533039078487377882099113092014071356307535
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/71.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1987167 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1987167 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1987167 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1987167 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1987167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

85.csrng_err.82512003316583311012176123492401300241821554437786628098302540490206641246474
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/85.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 30107277 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 30107277 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 30107277 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  30107277 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  30107277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 1 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

13.csrng_err.2301745098065427601408991842875806725346305375199219777073146552936086442421
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  13.csrng_err.2992443829
  
  coverage files:
    model(design data) :  /workspace/coverage/default/13.csrng_err.2992443829/icc_045766fd_29c39fee.ucm
    data               :  /workspace/coverage/default/13.csrng_err.2992443829/icc_045766fd_29c39fee.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jan 25, 2024 at 00:29:21 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

158.csrng_err.5206613404486367425546109237141704301950369453200418073072160956597060903876
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/158.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  158.csrng_err.164766660
  
  coverage files:
    model(design data) :  /workspace/coverage/default/158.csrng_err.164766660/icc_045766fd_29c39fee.ucm
    data               :  /workspace/coverage/default/158.csrng_err.164766660/icc_045766fd_29c39fee.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jan 25, 2024 at 02:30:31 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 8.csrng_stress_all.85459486825737363386847881759635781859810400498629712218798643546435744513728
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 18144490232 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 18144490232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 32.csrng_stress_all.82182522970582019885541228773450398482678448080291231652025507064600903595612
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5349234907 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5349234907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```