4ddd81322f
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | csrng_smoke | 0 | 50 | 0.00 | ||
V1 | csr_hw_reset | csrng_csr_hw_reset | 0 | 5 | 0.00 | ||
V1 | csr_rw | csrng_csr_rw | 0 | 20 | 0.00 | ||
V1 | csr_bit_bash | csrng_csr_bit_bash | 0 | 5 | 0.00 | ||
V1 | csr_aliasing | csrng_csr_aliasing | 0 | 5 | 0.00 | ||
V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 0 | 20 | 0.00 | ||
csrng_csr_aliasing | 0 | 5 | 0.00 | ||||
V1 | TOTAL | 0 | 105 | 0.00 | |||
V2 | interrupts | csrng_intr | 0 | 200 | 0.00 | ||
V2 | alerts | csrng_alert | 0 | 500 | 0.00 | ||
V2 | err | csrng_err | 0 | 500 | 0.00 | ||
V2 | cmds | csrng_cmds | 0 | 50 | 0.00 | ||
V2 | life cycle | csrng_cmds | 0 | 50 | 0.00 | ||
V2 | stress_all | csrng_stress_all | 0 | 50 | 0.00 | ||
V2 | intr_test | csrng_intr_test | 0 | 50 | 0.00 | ||
V2 | alert_test | csrng_alert_test | 0 | 50 | 0.00 | ||
V2 | tl_d_oob_addr_access | csrng_tl_errors | 0 | 20 | 0.00 | ||
V2 | tl_d_illegal_access | csrng_tl_errors | 0 | 20 | 0.00 | ||
V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 0 | 5 | 0.00 | ||
csrng_csr_rw | 0 | 20 | 0.00 | ||||
csrng_csr_aliasing | 0 | 5 | 0.00 | ||||
csrng_same_csr_outstanding | 0 | 20 | 0.00 | ||||
V2 | tl_d_partial_access | csrng_csr_hw_reset | 0 | 5 | 0.00 | ||
csrng_csr_rw | 0 | 20 | 0.00 | ||||
csrng_csr_aliasing | 0 | 5 | 0.00 | ||||
csrng_same_csr_outstanding | 0 | 20 | 0.00 | ||||
V2 | TOTAL | 0 | 1440 | 0.00 | |||
V2S | tl_intg_err | csrng_sec_cm | 0 | 5 | 0.00 | ||
csrng_tl_intg_err | 0 | 20 | 0.00 | ||||
V2S | sec_cm_config_regwen | csrng_regwen | 0 | 50 | 0.00 | ||
csrng_csr_rw | 0 | 20 | 0.00 | ||||
V2S | sec_cm_config_mubi | csrng_alert | 0 | 500 | 0.00 | ||
V2S | sec_cm_intersig_mubi | csrng_stress_all | 0 | 50 | 0.00 | ||
V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_update_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_ctrl_mubi | csrng_alert | 0 | 500 | 0.00 | ||
V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
V2S | sec_cm_constants_lc_gated | csrng_stress_all | 0 | 50 | 0.00 | ||
V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 0 | 500 | 0.00 | ||
V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 0 | 20 | 0.00 | ||
V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
csrng_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 0 | 200 | 0.00 | ||
csrng_err | 0 | 500 | 0.00 | ||||
V2S | TOTAL | 0 | 75 | 0.00 | |||
V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 0 | 1670 | 0.00 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 0 | 0.00 |
V2 | 9 | 9 | 0 | 0.00 |
V2S | 3 | 3 | 0 | 0.00 |
V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed.
has 1672 failures:
0.csrng_smoke.67289719916747925054630555214881950033040574217776411882742397065822657632867
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_smoke/latest/run.log
1.csrng_smoke.23631867392217521055060607687207041189918384910801099570487850513186806514902
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_smoke/latest/run.log
... and 48 more failures.
0.csrng_cmds.70795668902357856137057195198244044510148451180803587209334449714725630728336
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_cmds/latest/run.log
1.csrng_cmds.26623574897149756630999683034352257415848741002782850648819347425841401609109
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_cmds/latest/run.log
... and 48 more failures.
0.csrng_stress_all.93310103657119157831517987785772813722512792945327367995771140169235412020936
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
1.csrng_stress_all.100982841768960768145062269254226783596183817311954571106830844202160310888573
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
... and 48 more failures.
0.csrng_intr.62102828756711753492604818512247065468232800180827459738919530853900901225396
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_intr/latest/run.log
1.csrng_intr.39508505664495100759960421436984518473763583052365141913037938753427185845563
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_intr/latest/run.log
... and 198 more failures.
0.csrng_alert.5623848584425078172180271147923068318603127352368243186595894341921550649840
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_alert/latest/run.log
1.csrng_alert.55736603429499294217688386200516181212321852391408451776729405815803757180672
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_alert/latest/run.log
... and 498 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.