CSRNG Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	231.218us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	78.866us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	49.109us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	38.000s	3.209ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	327.985us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	59.086us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	49.109us	20	20	100.00
		csrng_csr_aliasing	6.000s	327.985us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	298.988us	200	200	100.00
V2	alerts	csrng_alert	9.000s	550.243us	500	500	100.00
V2	err	csrng_err	5.000s	29.820us	487	500	97.40
V2	cmds	csrng_cmds	7.567m	27.467ms	50	50	100.00
V2	life cycle	csrng_cmds	7.567m	27.467ms	50	50	100.00
V2	stress_all	csrng_stress_all	40.000m	199.002ms	45	50	90.00
V2	intr_test	csrng_intr_test	13.000s	41.650us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	235.291us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	706.828us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	706.828us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	78.866us	5	5	100.00
		csrng_csr_rw	8.000s	49.109us	20	20	100.00
		csrng_csr_aliasing	6.000s	327.985us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	42.743us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	78.866us	5	5	100.00
		csrng_csr_rw	8.000s	49.109us	20	20	100.00
		csrng_csr_aliasing	6.000s	327.985us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	42.743us	20	20	100.00
V2		TOTAL			1422	1440	98.75
V2S	tl_intg_err	csrng_sec_cm	8.000s	215.588us	5	5	100.00
		csrng_tl_intg_err	13.000s	604.587us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	36.666us	50	50	100.00
		csrng_csr_rw	8.000s	49.109us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	9.000s	550.243us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	40.000m	199.002ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	9.000s	550.243us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	40.000m	199.002ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	9.000s	550.243us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	604.587us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
		csrng_sec_cm	8.000s	215.588us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	298.988us	200	200	100.00
		csrng_err	5.000s	29.820us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.050h	46.217ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1602	1670	95.93

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.66	93.18	84.17	95.30	86.30	92.00	98.18	97.50	94.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:789) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test csrng_stress_all_with_rand_reset has 35 failures.
  - 1.csrng_stress_all_with_rand_reset.113278104054901006583612156927463542716385218934822640624620545819680192387594
    Line 396, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19326512720 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19326512720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.74293609118068542259424282024853836117181294419788904959017142114446001520480
    Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26636546710 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26636546710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:789) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test csrng_stress_all_with_rand_reset has 15 failures.
  - 0.csrng_stress_all_with_rand_reset.4588732834096477937566915353928410851783536036096123123812535546313580358126
    Line 382, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34507532113 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34507532113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.23401225859483906345070360881541075533368425346462118786675935241865580502120
    Line 293, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1826565574 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1826565574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed

has 6 failures:

Test csrng_err has 6 failures.

116.csrng_err.103845347222710963220615403978635113856620733801340229942948727244475216176107
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/116.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 15157440 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 15157440 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 15157440 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  15157440 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  15157440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

170.csrng_err.65597700864672581644971569613450910196155315457517714570512485646920945088936
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/170.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 21401170 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 21401170 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 21401170 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  21401170 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  21401170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed

has 6 failures:

Test csrng_err has 6 failures.

122.csrng_err.14907835652768832743150428304043096009255677012293292173801929682542337656475
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/122.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 2088992 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2088992 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2088992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

129.csrng_err.28756373382294408958908684588186785805668661462157877755696256691439814954627
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/129.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3117127 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3117127 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3117127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 5 failures:
- Test csrng_stress_all has 5 failures.
  - 8.csrng_stress_all.1995023550536417115775819597287800006069610885534244332064073675088237574611
    Line 358, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4883628135 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4883628135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.csrng_stress_all.20103239501692308123075245094663232202870616075193497508468536556617598100590
    Line 315, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 9368769580 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 9368769580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

248.csrng_err.46558626951547837524312378224457483802529946368889920621489999256158813388270
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/248.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  248.csrng_err.2849340910
  
  coverage files:
    model(design data) :  /workspace/coverage/default/248.csrng_err.2849340910/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/248.csrng_err.2849340910/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Feb 29, 2024 at 14:18:52 PST  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1