CSRNG Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: `32ed2c4230`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	145.169us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	38.321us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	25.064us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	21.000s	662.455us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	162.897us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	448.634us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	25.064us	20	20	100.00
		csrng_csr_aliasing	5.000s	162.897us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	308.757us	200	200	100.00
V2	alerts	csrng_alert	8.000s	514.657us	500	500	100.00
V2	err	csrng_err	5.000s	37.099us	487	500	97.40
V2	cmds	csrng_cmds	8.733m	52.834ms	50	50	100.00
V2	life cycle	csrng_cmds	8.733m	52.834ms	50	50	100.00
V2	stress_all	csrng_stress_all	18.400m	59.442ms	43	50	86.00
V2	intr_test	csrng_intr_test	8.000s	15.278us	50	50	100.00
V2	alert_test	csrng_alert_test	4.000s	18.327us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	234.126us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	234.126us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	38.321us	5	5	100.00
		csrng_csr_rw	4.000s	25.064us	20	20	100.00
		csrng_csr_aliasing	5.000s	162.897us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	652.106us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	38.321us	5	5	100.00
		csrng_csr_rw	4.000s	25.064us	20	20	100.00
		csrng_csr_aliasing	5.000s	162.897us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	652.106us	20	20	100.00
V2		TOTAL			1420	1440	98.61
V2S	tl_intg_err	csrng_sec_cm	12.000s	201.978us	5	5	100.00
		csrng_tl_intg_err	29.000s	1.879ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	20.161us	50	50	100.00
		csrng_csr_rw	4.000s	25.064us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	8.000s	514.657us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	18.400m	59.442ms	43	50	86.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	8.000s	514.657us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	18.400m	59.442ms	43	50	86.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	8.000s	514.657us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	29.000s	1.879ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
		csrng_sec_cm	12.000s	201.978us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	308.757us	200	200	100.00
		csrng_err	5.000s	37.099us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.867h	376.329ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1600	1670	95.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.72	93.20	84.21	95.34	86.30	92.00	100.00	97.50	95.50

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:789) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test csrng_stress_all_with_rand_reset has 36 failures.
  - 0.csrng_stress_all_with_rand_reset.56585729982228131589232516555853699300432002576955403610635498275036632856355
    Line 455, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 162720316021 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 162720316021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.5808620122092852317789695035999041363929637588133329559467408720163998447678
    Line 333, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9980443210 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9980443210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:789) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test csrng_stress_all_with_rand_reset has 14 failures.
  - 2.csrng_stress_all_with_rand_reset.45896656180026847015152788692324300734853811535277475029816728763065711220047
    Line 295, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3737780552 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3737780552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all_with_rand_reset.60859537808956996653566773637959794806527989893777897914978220824866302967147
    Line 355, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23847902307 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23847902307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed

has 7 failures:

Test csrng_err has 7 failures.

2.csrng_err.108340867687557236991716638032798918612718841135009339312937045523457908988403
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3596291 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3596291 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3596291 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3596291 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3596291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

160.csrng_err.25459899004915249318610176431358216944615630859485001350380167948281902346225
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/160.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3249356 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3249356 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3249356 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3249356 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3249356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:
- Test csrng_stress_all has 4 failures.
  - 5.csrng_stress_all.102014410848688267805171201191716487582882940304523832273875283654997723580836
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 6219122701 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 6219122701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.csrng_stress_all.68514310376094962629346260100909234098223616083546168292002762955884817919332
    Line 305, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  18996856 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  18996856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed

has 4 failures:

Test csrng_err has 4 failures.

29.csrng_err.92454221634534792207906353028604964467859367851694643416146465113281958479078
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3114195 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3114195 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3114195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

144.csrng_err.8823375377472581766325867886485846497129349051252973868512341413161690607232
Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/144.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3776424 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3776424 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3776424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 15.csrng_stress_all.111750932770263480050978667417294892341430612483289409685374420215428743526528
    Line 306, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 143762608 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 143762608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.csrng_stress_all.61012603442763557164793011742922027085903325250802009614126879245724754908605
    Line 328, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 6597089554 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 6597089554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

46.csrng_err.93233144397272182517891980577473395853847160803861015480383911242984713664469
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  46.csrng_err.4186486741
  
  coverage files:
    model(design data) :  /workspace/coverage/default/46.csrng_err.4186486741/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/46.csrng_err.4186486741/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Feb 28, 2024 at 18:19:40 PST  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

286.csrng_err.77266881446271972262433104215201173509670720291887605213853258770799667279297
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/286.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  286.csrng_err.3904730561
  
  coverage files:
    model(design data) :  /workspace/coverage/default/286.csrng_err.3904730561/icc_56faddb5_0cd6eabc.ucm
    data               :  /workspace/coverage/default/286.csrng_err.3904730561/icc_56faddb5_0cd6eabc.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Feb 28, 2024 at 18:22:48 PST  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1