CSRNG Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	19.000s	31.888us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	42.632us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	34.183us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	37.000s	3.600ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	25.886us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	120.998us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	34.183us	20	20	100.00
		csrng_csr_aliasing	5.000s	25.886us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	68.764us	186	200	93.00
V2	alerts	csrng_alert	20.000s	53.470us	500	500	100.00
V2	err	csrng_err	18.000s	21.034us	491	500	98.20
V2	cmds	csrng_cmds	8.350m	50.456ms	50	50	100.00
V2	life cycle	csrng_cmds	8.350m	50.456ms	50	50	100.00
V2	stress_all	csrng_stress_all	33.533m	112.158ms	49	50	98.00
V2	intr_test	csrng_intr_test	5.000s	70.407us	50	50	100.00
V2	alert_test	csrng_alert_test	14.000s	132.361us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.401ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.401ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	42.632us	5	5	100.00
		csrng_csr_rw	4.000s	34.183us	20	20	100.00
		csrng_csr_aliasing	5.000s	25.886us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	249.752us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	42.632us	5	5	100.00
		csrng_csr_rw	4.000s	34.183us	20	20	100.00
		csrng_csr_aliasing	5.000s	25.886us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	249.752us	20	20	100.00
V2		TOTAL			1416	1440	98.33
V2S	tl_intg_err	csrng_sec_cm	17.000s	148.054us	5	5	100.00
		csrng_tl_intg_err	34.000s	1.956ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	10.642us	50	50	100.00
		csrng_csr_rw	4.000s	34.183us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	20.000s	53.470us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	33.533m	112.158ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	20.000s	53.470us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	33.533m	112.158ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	20.000s	53.470us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	34.000s	1.956ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
		csrng_sec_cm	17.000s	148.054us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	68.764us	186	200	93.00
		csrng_err	18.000s	21.034us	491	500	98.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	56.283m	156.474ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1596	1670	95.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.84	93.24	84.51	95.24	80.09	91.81	100.00	97.55	93.31

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
- Test csrng_stress_all_with_rand_reset has 30 failures.
  - 0.csrng_stress_all_with_rand_reset.66409516109193044336563194921120351783037607933178668025447851860119031339708
    Line 345, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17416187910 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17416187910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.37267147579176812908731509222182982304493167355347080516270546968261803754850
    Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52916436533 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 52916436533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test csrng_stress_all_with_rand_reset has 20 failures.
  - 2.csrng_stress_all_with_rand_reset.95101624857021202497914525831211754099911472462659525229220238718489538126601
    Line 395, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9110124674 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9110124674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.18747245012266264774348186133087178129566099095624665320157953047815863909144
    Line 359, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8065109309 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8065109309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,440): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 12 failures:

Test csrng_intr has 12 failures.

29.csrng_intr.41736815291498548606299357762102347242946255284720411700299079257976528259001
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,440): (time 40804014 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  40804014 ps: (csrng_cmd_stage.sv:440) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  40804014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.csrng_intr.87594399332268081235815029456362965264578098440079522690166030856370704309032
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,440): (time 16258748 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  16258748 ps: (csrng_cmd_stage.sv:440) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  16258748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

26.csrng_err.40631435247465688163272948636683329477296044430343150178687910188436932872544
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 6130139 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   6130139 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   6130139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

155.csrng_err.17160344691753827117915950582702051153198668924447787291857468464949818581244
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/155.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 5275391 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   5275391 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   5275391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

30.csrng_err.106631435697740983941044653738253759379721798892408282616578863855399077272634
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5625427 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5625427 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5625427 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   5625427 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   5625427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

211.csrng_err.25903391636985533889867598677600124306421610142959445617782078248713483979087
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/211.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 18404447 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 18404447 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 18404447 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  18404447 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  18404447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1737): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

51.csrng_intr.77037517718801643609145594458118105276120170957954390330979704755154651125732
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/51.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1737): (time 26382244 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1738): (time 26382244 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  26382244 ps: (csrng_core.sv:1737) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  26382244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

138.csrng_intr.96056624905637561634376898095571787720842384659541525509849638777208050337662
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/138.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1737): (time 23806127 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1738): (time 23806127 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  23806127 ps: (csrng_core.sv:1737) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  23806127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 34.csrng_stress_all.95388479464943525614216114890974707974832361350218709175278092379070567249658
    Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 104288248 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 104288248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 92.csrng_err.63073008945552882012530532854458699813533876921608434459468747452817945605099
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/92.csrng_err/latest/run.log
```
  UVM_ERROR @  25204179 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  25204179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```