CSRNG Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: `9656691e03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	167.241us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	28.847us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	19.891us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	23.000s	776.515us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	48.558us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	11.000s	88.535us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	19.891us	20	20	100.00
		csrng_csr_aliasing	5.000s	48.558us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	254.120us	178	200	89.00
V2	alerts	csrng_alert	7.000s	448.073us	500	500	100.00
V2	err	csrng_err	5.000s	20.199us	484	500	96.80
V2	cmds	csrng_cmds	9.333m	57.987ms	50	50	100.00
V2	life cycle	csrng_cmds	9.333m	57.987ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.917m	69.455ms	48	50	96.00
V2	intr_test	csrng_intr_test	8.000s	50.448us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	203.271us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	714.731us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	714.731us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	28.847us	5	5	100.00
		csrng_csr_rw	6.000s	19.891us	20	20	100.00
		csrng_csr_aliasing	5.000s	48.558us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	30.117us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	28.847us	5	5	100.00
		csrng_csr_rw	6.000s	19.891us	20	20	100.00
		csrng_csr_aliasing	5.000s	48.558us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	30.117us	20	20	100.00
V2		TOTAL			1400	1440	97.22
V2S	tl_intg_err	csrng_sec_cm	6.000s	235.211us	5	5	100.00
		csrng_tl_intg_err	11.000s	247.637us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	194.124us	50	50	100.00
		csrng_csr_rw	6.000s	19.891us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	7.000s	448.073us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.917m	69.455ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	7.000s	448.073us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.917m	69.455ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	7.000s	448.073us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	247.637us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
		csrng_sec_cm	6.000s	235.211us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	254.120us	178	200	89.00
		csrng_err	5.000s	20.199us	484	500	96.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.826h	664.472ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1580	1670	94.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.43	92.89	83.80	94.64	80.10	91.81	100.00	97.55	92.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
- Test csrng_stress_all_with_rand_reset has 36 failures.
  - 0.csrng_stress_all_with_rand_reset.32388895621967751164844324089401877152458780909345439182974358796350403111959
    Line 377, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 54656275317 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 54656275317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.65701484729466376040734613289698526069814656766919873532914703521815613317011
    Line 291, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1998117507 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1998117507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 34 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 18 failures:

Test csrng_intr has 18 failures.

10.csrng_intr.75728035377180381167688097316447333267425538721443197889421924302917924547171
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 10774324 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  10774324 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  10774324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.csrng_intr.70936084684838785197116724570412916158167067346707292395018769727706408800241
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 26619371 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  26619371 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  26619371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test csrng_stress_all_with_rand_reset has 14 failures.
  - 5.csrng_stress_all_with_rand_reset.92796070904179325861573972558411214463663595077469408684505840590922203586137
    Line 317, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4303008785 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4303008785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all_with_rand_reset.73916214701682308472896852111770204790516576122400563642802800722075301352108
    Line 474, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112388730990 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 112388730990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 8 failures:

Test csrng_err has 8 failures.

13.csrng_err.47882832185287613277029128542240534918039459122489141321344471174253990254712
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1579763 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1579763 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1579763 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1579763 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1579763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

116.csrng_err.34923393075479133017943300746197160782448035001926150066312433558642940668993
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/116.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 12828113 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 12828113 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 12828113 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @  12828113 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @  12828113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 6 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:

Test csrng_err has 5 failures.

232.csrng_err.96735083582299957620556008988883307353206420682503931269729766572320821609016
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/232.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  232.csrng_err.1377567288
  
  coverage files:
    model(design data) :  /workspace/coverage/default/232.csrng_err.1377567288/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/232.csrng_err.1377567288/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 09, 2024 at 14:23:04 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

247.csrng_err.6317247607131541474235585600388624525774450979091474166293086839614462241479
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/247.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  247.csrng_err.2544380615
  
  coverage files:
    model(design data) :  /workspace/coverage/default/247.csrng_err.2544380615/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/247.csrng_err.2544380615/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 09, 2024 at 14:23:17 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

57.csrng_intr.23995452589191433230161122391400062514569317388103002122191527347811867702054
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/57.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 13512324 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 13512324 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  13512324 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  13512324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

112.csrng_intr.80191987856511180531194012819823566381277234502221438282672630760307292497925
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/112.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 21717441 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 21717441 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  21717441 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  21717441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 3 failures:

Test csrng_err has 3 failures.

241.csrng_err.45324315222687752921932947829706974757669291485333577082291004740989343592849
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/241.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2870580 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2870580 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2870580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

320.csrng_err.87450116069686507181525201546126036643909932810242965542303957077641483335352
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/320.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 9445373 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   9445373 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   9445373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 1.csrng_stress_all.54770756189310796321982645016902209978877767926958485568257348745221010361227
    Line 327, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4458753922 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4458753922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 15.csrng_stress_all.19686608070687970046495919261028703510323149198775133144273767568475565745073
    Line 338, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4487465333 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4487465333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```