CSRNG Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	149.611us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	34.710us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	18.869us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	30.000s	1.619ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	57.293us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	421.241us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	18.869us	20	20	100.00
		csrng_csr_aliasing	5.000s	57.293us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	267.585us	179	200	89.50
V2	alerts	csrng_alert	42.000s	3.759ms	500	500	100.00
V2	err	csrng_err	14.000s	97.378us	484	500	96.80
V2	cmds	csrng_cmds	10.117m	32.854ms	49	50	98.00
V2	life cycle	csrng_cmds	10.117m	32.854ms	49	50	98.00
V2	stress_all	csrng_stress_all	23.283m	111.463ms	50	50	100.00
V2	intr_test	csrng_intr_test	5.000s	228.832us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	13.839us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	689.882us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	689.882us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	34.710us	5	5	100.00
		csrng_csr_rw	5.000s	18.869us	20	20	100.00
		csrng_csr_aliasing	5.000s	57.293us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	348.097us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	34.710us	5	5	100.00
		csrng_csr_rw	5.000s	18.869us	20	20	100.00
		csrng_csr_aliasing	5.000s	57.293us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	348.097us	20	20	100.00
V2		TOTAL			1402	1440	97.36
V2S	tl_intg_err	csrng_sec_cm	8.000s	136.779us	5	5	100.00
		csrng_tl_intg_err	14.000s	1.430ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	33.198us	50	50	100.00
		csrng_csr_rw	5.000s	18.869us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	42.000s	3.759ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	23.283m	111.463ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	42.000s	3.759ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	23.283m	111.463ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	42.000s	3.759ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	1.430ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
		csrng_sec_cm	8.000s	136.779us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	267.585us	179	200	89.50
		csrng_err	14.000s	97.378us	484	500	96.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.146h	172.127ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1582	1670	94.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.94	93.40	85.01	95.32	80.53	91.81	100.00	97.55	90.92

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test csrng_stress_all_with_rand_reset has 35 failures.
  - 1.csrng_stress_all_with_rand_reset.56163412922762558674779617606009740023198731689475881754063767351860023235849
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11429394879 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11429394879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.37981695156247391572818433489481030538557793668168461871649140439637429734730
    Line 390, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8411689170 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8411689170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 18 failures:

Test csrng_intr has 18 failures.

7.csrng_intr.41472939015444228143775595682990928432186111573980233203856587960899945140281
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 44264850 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  44264850 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  44264850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.csrng_intr.78013802465204732841599058061437455278277147008675182011732026150633423145694
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 10372971 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  10372971 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  10372971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
- Test csrng_stress_all_with_rand_reset has 15 failures.
  - 0.csrng_stress_all_with_rand_reset.113414425457866997642405231363292729036841067823075943257123419702122651093197
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10843831390 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10843831390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.53557169645631024234247249981195134623425501445867903397239380065633821712309
    Line 527, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23025017749 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23025017749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 7 failures:

Test csrng_err has 7 failures.

59.csrng_err.27437300099494403888934252000779383598612235754047611213718449979703807337336
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/59.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3221206 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3221206 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3221206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

70.csrng_err.95614775814080593199368166859855369891857152661261061466623954175595057715919
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/70.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3390174 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3390174 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3390174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

89.csrng_err.60062760059312425279810699810621170018792703130863778334611426517798367170316
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/89.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 2330311 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 2330311 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 2330311 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   2330311 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   2330311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

103.csrng_err.19473641151289821008773293429839428690680462214249585580989105538704611340719
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/103.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3044166 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3044166 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3044166 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3044166 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3044166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

42.csrng_intr.72197124629598202753340027547261511620843544951117829351221979088700953994486
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/42.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 12141384 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 12141384 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1724): (time 12141384 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1725): (time 12141384 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 12141384 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed

91.csrng_intr.16326286505183310080944370700631710449282308236622738100628283922307850664438
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/91.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 47269008 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 47269008 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  47269008 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  47269008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

158.csrng_err.59985788348320136676485579201260486554539683629754792426319571984913063541600
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/158.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  158.csrng_err.736426848
  
  coverage files:
    model(design data) :  /workspace/coverage/default/158.csrng_err.736426848/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/158.csrng_err.736426848/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 28, 2024 at 12:59:03 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

485.csrng_err.13574178843238552725362049777760117299645058893283511109105344040866986122050
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/485.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  485.csrng_err.168876866
  
  coverage files:
    model(design data) :  /workspace/coverage/default/485.csrng_err.168876866/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/485.csrng_err.168876866/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 28, 2024 at 13:00:56 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

UVM_FATAL (csrng_env_cfg.sv:282) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 30.csrng_cmds.26637698366778234641802333787282793096898503521580976230374783379414469497295
    Line 364, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 5068317378 ps: (csrng_env_cfg.sv:282) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 5068317378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 236.csrng_err.79820841884731454341786060887530509922589875746056604826865681824029137935034
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/236.csrng_err/latest/run.log
```
  UVM_ERROR @   5818260 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   5818260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```