CSRNG Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	102.749us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	13.000s	43.888us	5	5	100.00
V1	csr_rw	csrng_csr_rw	14.000s	20.900us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	23.000s	715.755us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	17.000s	200.567us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	13.000s	30.188us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	14.000s	20.900us	20	20	100.00
		csrng_csr_aliasing	17.000s	200.567us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	29.743us	176	200	88.00
V2	alerts	csrng_alert	1.400m	7.895ms	500	500	100.00
V2	err	csrng_err	18.000s	19.862us	493	500	98.60
V2	cmds	csrng_cmds	9.117m	56.908ms	49	50	98.00
V2	life cycle	csrng_cmds	9.117m	56.908ms	49	50	98.00
V2	stress_all	csrng_stress_all	16.283m	11.920ms	48	50	96.00
V2	intr_test	csrng_intr_test	9.000s	59.736us	50	50	100.00
V2	alert_test	csrng_alert_test	14.000s	42.778us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1.255ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1.255ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	13.000s	43.888us	5	5	100.00
		csrng_csr_rw	14.000s	20.900us	20	20	100.00
		csrng_csr_aliasing	17.000s	200.567us	5	5	100.00
		csrng_same_csr_outstanding	12.000s	384.151us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	13.000s	43.888us	5	5	100.00
		csrng_csr_rw	14.000s	20.900us	20	20	100.00
		csrng_csr_aliasing	17.000s	200.567us	5	5	100.00
		csrng_same_csr_outstanding	12.000s	384.151us	20	20	100.00
V2		TOTAL			1406	1440	97.64
V2S	tl_intg_err	csrng_sec_cm	11.000s	367.742us	5	5	100.00
		csrng_tl_intg_err	15.000s	1.367ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	56.163us	50	50	100.00
		csrng_csr_rw	14.000s	20.900us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.400m	7.895ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	16.283m	11.920ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.400m	7.895ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	16.283m	11.920ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.400m	7.895ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	1.367ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
		csrng_sec_cm	11.000s	367.742us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	29.743us	176	200	88.00
		csrng_err	18.000s	19.862us	493	500	98.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	49.633m	99.403ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1586	1670	94.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.92	93.40	85.01	95.32	80.56	91.81	100.00	97.39	90.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
- Test csrng_stress_all_with_rand_reset has 37 failures.
  - 0.csrng_stress_all_with_rand_reset.75277791890873325477446139179112685796693618425121396350099000971776510829905
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 326185784 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 326185784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.109335916193763139907894734510678149994656548345018154163953499553246379961036
    Line 344, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19552384151 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19552384151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 17 failures:

Test csrng_intr has 17 failures.

0.csrng_intr.37403994197612179940827073738750308829503518136338999497418451883652132726738
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 169756261 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 169756261 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 169756261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.csrng_intr.37666890501932273499071411557732028937498616882897577380608692651519194299020
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 42669604 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  42669604 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  42669604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test csrng_stress_all_with_rand_reset has 13 failures.
  - 5.csrng_stress_all_with_rand_reset.21327380898347147925985597195206260389969878211420094739067169099100841683366
    Line 283, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3701342925 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3701342925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.csrng_stress_all_with_rand_reset.42183410208114030935839232818878618830697607906416256598830923307069812412504
    Line 621, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 99402548853 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 99402548853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 6 failures:

Test csrng_intr has 6 failures.

74.csrng_intr.64241739720315796627062762085062366782235396643702685474831813113751913361557
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/74.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 14289801 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 14289801 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  14289801 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  14289801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

124.csrng_intr.15687272701976571047921594471265872572209135357093626075882797841469959518307
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/124.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 40420713 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 40420713 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  40420713 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  40420713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

246.csrng_err.1571065545313539605459299854364193498034701162884661192125148145481977380494
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/246.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 3009797 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 3009797 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 3009797 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   3009797 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   3009797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

288.csrng_err.45686041642013378935602593550218196051313457270236705449558091667437181447981
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/288.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4184865 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4184865 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4184865 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4184865 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4184865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 11.csrng_stress_all.109766207162689348714050518825102846204652096216803141158359023199192001707624
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  10255563 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  10255563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.csrng_stress_all.24232249619257788334273251888903270073670188921341755654589334700635853100540
    Line 315, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/45.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3176182083 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3176182083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

15.csrng_err.35169705774964965229406639862955357162996548371566628870416070128277361142034
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  15.csrng_err.789719314
  
  coverage files:
    model(design data) :  /workspace/coverage/default/15.csrng_err.789719314/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/15.csrng_err.789719314/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 30, 2024 at 12:31:41 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

325.csrng_err.115658027486443733087508366642625389513959891533753538016800043824695392439702
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/325.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  325.csrng_err.230788502
  
  coverage files:
    model(design data) :  /workspace/coverage/default/325.csrng_err.230788502/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/325.csrng_err.230788502/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 30, 2024 at 12:33:56 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

UVM_FATAL (csrng_env_cfg.sv:283) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 3.csrng_cmds.101148685986291021729875226941966181885813970492255084479668497494489414243474
    Line 394, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 11559163704 ps: (csrng_env_cfg.sv:283) [cfg] Check failed hw_v == v[app] (302996629061264872801420961387126611540 [0xe3f30731486f9590dba56c2c58ba5e54] vs 0 [0x0])
  UVM_INFO @ 11559163704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1721): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

40.csrng_intr.50179162002395575881268965114702485860188135863302942313916294434884880426384
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/40.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1721): (time 15403870 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 15403870 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 15403870 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1724): (time 15403870 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1725): (time 15403870 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 1 failures:
- Test csrng_err has 1 failures.
  - 362.csrng_err.7712770817803302041202023811219754803460355141852307627607116065894022110723
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/362.csrng_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 7676173 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7676173 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7676173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```