CSRNG Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	39.237us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	46.017us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	142.698us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	16.000s	258.465us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	150.706us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	110.810us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	142.698us	20	20	100.00
		csrng_csr_aliasing	5.000s	150.706us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	48.652us	182	200	91.00
V2	alerts	csrng_alert	53.000s	3.852ms	500	500	100.00
V2	err	csrng_err	14.000s	37.148us	487	500	97.40
V2	cmds	csrng_cmds	5.850m	33.914ms	50	50	100.00
V2	life cycle	csrng_cmds	5.850m	33.914ms	50	50	100.00
V2	stress_all	csrng_stress_all	14.800m	37.169ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	11.618us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	26.715us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	17.000s	956.561us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	17.000s	956.561us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	46.017us	5	5	100.00
		csrng_csr_rw	5.000s	142.698us	20	20	100.00
		csrng_csr_aliasing	5.000s	150.706us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	49.670us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	46.017us	5	5	100.00
		csrng_csr_rw	5.000s	142.698us	20	20	100.00
		csrng_csr_aliasing	5.000s	150.706us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	49.670us	20	20	100.00
V2		TOTAL			1408	1440	97.78
V2S	tl_intg_err	csrng_sec_cm	7.000s	247.776us	5	5	100.00
		csrng_tl_intg_err	20.000s	1.052ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	29.975us	50	50	100.00
		csrng_csr_rw	5.000s	142.698us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	53.000s	3.852ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	14.800m	37.169ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	53.000s	3.852ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	14.800m	37.169ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	53.000s	3.852ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	20.000s	1.052ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
		csrng_sec_cm	7.000s	247.776us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	48.652us	182	200	91.00
		csrng_err	14.000s	37.148us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.354h	59.346ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1588	1670	95.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
91.92	93.38	84.97	95.28	80.53	91.81	100.00	97.55	91.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
- Test csrng_stress_all_with_rand_reset has 28 failures.
  - 0.csrng_stress_all_with_rand_reset.97816230679101915093789624076000207724528931075186024550746517509334858395124
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31628688299 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31628688299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.36930299658382103428834194331645088691072842708703342999332408020840790471232
    Line 299, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10040611832 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10040611832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 26 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test csrng_stress_all_with_rand_reset has 22 failures.
  - 1.csrng_stress_all_with_rand_reset.21508862015419277154056069455994335316153769239203275522051368166782359387765
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 21788346677 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 21788346677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.52389485373740965327327291434750481088931588522366226753713494943515639212149
    Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36195770331 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 36195770331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 14 failures:

Test csrng_intr has 14 failures.

7.csrng_intr.6546564232973861160487547773791201330093004569246418290312882967026582272446
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 13034399 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  13034399 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  13034399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.csrng_intr.61976977571979066875932807694408508432785314815455954254596239510261191302182
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 18944505 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  18944505 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  18944505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

43.csrng_err.18462929724129253525407512500097212032553201758555166563796982018334847860987
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4172423 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4172423 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4172423 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   4172423 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   4172423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

101.csrng_err.109920098693162886699083984559202465046763991453380989447523756763806382512590
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/101.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5919441 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5919441 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5919441 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   5919441 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   5919441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

34.csrng_intr.57602596726959514675204998982988633451841964374616274040669146566793159685649
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/34.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 15869263 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 15869263 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  15869263 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  15869263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

54.csrng_intr.469873642181968776955062885223485763129620758091111808808563555685690062959
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/54.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 43268134 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 43268134 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  43268134 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  43268134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 4 failures:

Test csrng_err has 4 failures.

227.csrng_err.105146037395120993924661925965421145042503534397982946628726868820480188807026
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/227.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3974682 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3974682 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3974682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

472.csrng_err.21865246641236080999748439011197682781860495085597570458845695376522684439644
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/472.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 7306584 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   7306584 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   7306584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

87.csrng_err.42837570635694211790051004713708555684405757961648752626557714730008940317004
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/87.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  87.csrng_err.218564940
  
  coverage files:
    model(design data) :  /workspace/coverage/default/87.csrng_err.218564940/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/87.csrng_err.218564940/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 26, 2024 at 12:28:27 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

209.csrng_err.23186717370036179617156731572312556469980288154450153995001493618327107910875
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/209.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  209.csrng_err.1244118235
  
  coverage files:
    model(design data) :  /workspace/coverage/default/209.csrng_err.1244118235/icc_7e55bc60_0e9d174d.ucm
    data               :  /workspace/coverage/default/209.csrng_err.1244118235/icc_7e55bc60_0e9d174d.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on May 26, 2024 at 12:29:20 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 17.csrng_stress_all.110620923140352522873716423781605382101783192749603838657212215071954961922319
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 2686530985 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2686530985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 212.csrng_err.90115135030268183694490864712925308671018323951534321644242298292576952885376
    Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/212.csrng_err/latest/run.log
```
  UVM_ERROR @   5365147 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   5365147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```