1579f6a912| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 5.000s | 138.517us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 187.155us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 3.000s | 22.222us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 22.000s | 361.789us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 6.000s | 354.133us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 6.000s | 342.744us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 3.000s | 22.222us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 6.000s | 354.133us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| V2 | alerts | csrng_alert | 1.250m | 6.870ms | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 |
| V2 | cmds | csrng_cmds | 6.067m | 25.298ms | 50 | 50 | 100.00 |
| V2 | life cycle | csrng_cmds | 6.067m | 25.298ms | 50 | 50 | 100.00 |
| V2 | stress_all | csrng_stress_all | 27.583m | 59.900ms | 49 | 50 | 98.00 |
| V2 | intr_test | csrng_intr_test | 4.000s | 62.165us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 4.000s | 57.028us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 14.000s | 751.292us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 14.000s | 751.292us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 187.155us | 5 | 5 | 100.00 |
| csrng_csr_rw | 3.000s | 22.222us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 6.000s | 354.133us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 85.943us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 187.155us | 5 | 5 | 100.00 |
| csrng_csr_rw | 3.000s | 22.222us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 6.000s | 354.133us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 85.943us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1400 | 1440 | 97.22 | |||
| V2S | tl_intg_err | csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 10.000s | 486.142us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 4.000s | 13.283us | 50 | 50 | 100.00 |
| csrng_csr_rw | 3.000s | 22.222us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 1.250m | 6.870ms | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 27.583m | 59.900ms | 49 | 50 | 98.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 1.250m | 6.870ms | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 27.583m | 59.900ms | 49 | 50 | 98.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 1.250m | 6.870ms | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 10.000s | 486.142us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| csrng_sec_cm | 6.000s | 231.261us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 6.000s | 208.914us | 178 | 200 | 89.00 |
| csrng_err | 9.000s | 37.180us | 483 | 500 | 96.60 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 1.949h | 300.552ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 1580 | 1670 | 94.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 6 | 66.67 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 91.94 | 93.40 | 85.01 | 95.32 | 80.56 | 91.81 | 100.00 | 97.39 | 91.03 |
UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:
0.csrng_stress_all_with_rand_reset.12158037567358974206580896642346669815780559158573296880491913730894422823365
Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 590174118 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 590174118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.csrng_stress_all_with_rand_reset.108573159525639141380840849521447069747209645620951025480492747924371790980292
Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 24857019020 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 24857019020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 35 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,503): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 17 failures:
3.csrng_intr.36204944293847693882234499602877851429225272648619037177762617428283469899406
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 26252885 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 26252885 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 26252885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.csrng_intr.112196537228416327326792575681769667524754529960595521080805976061491409327048
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,503): (time 151107155 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[0].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
UVM_ERROR @ 151107155 ps: (csrng_cmd_stage.sv:503) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
UVM_INFO @ 151107155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
5.csrng_stress_all_with_rand_reset.37499104909080997077217380837981537843939866069920955687230347457348344283383
Line 337, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9487789268 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9487789268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.csrng_stress_all_with_rand_reset.49798754598603038308954885645526289140318495542660981665865702772574092656842
Line 333, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8195570479 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8195570479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 6 failures:
152.csrng_err.7570387246543407728493642002811218116492929377876804849753759591842943369465
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/152.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 5604257 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 5604257 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 5604257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
201.csrng_err.85534887922832884547630508749469241823476731006802413226411241498069093404558
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/201.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 2258975 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 2258975 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2258975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1722): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:
11.csrng_intr.15034400153254452729166393804155444983937969580976946840407245443948525077028
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 15104511 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 15104511 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 15104511 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 15104511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
54.csrng_intr.76029131022100883909547702652997797894503799787209502103529218414587638911123
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/54.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 14113101 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 14113101 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
UVM_ERROR @ 14113101 ps: (csrng_core.sv:1722) [ASSERT FAILED] CsrngUniZeroizeKey_A
UVM_INFO @ 14113101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:
19.csrng_err.51624324306962317467785526521671338469124441794073567033057363919965783885569
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 4210104 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 4210104 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 4210104 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 4210104 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 4210104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
294.csrng_err.41952190263458810433967279422509022411115816925168002666311033966720518438885
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/294.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 14465262 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 14465262 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 14465262 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 14465262 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 14465262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 2 more failures.
Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:
140.csrng_err.103923767450815386508148602674416014961745671435131792476326983483283415758784
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/140.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 140.csrng_err.2438985664
coverage files:
model(design data) : /workspace/coverage/default/140.csrng_err.2438985664/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/140.csrng_err.2438985664/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 23, 2024 at 13:08:53 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1
264.csrng_err.38016034049059183229865904736458946964707206213085585187480854286940803017176
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/264.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 264.csrng_err.4130449880
coverage files:
model(design data) : /workspace/coverage/default/264.csrng_err.4130449880/icc_7e55bc60_0e9d174d.ucm
data : /workspace/coverage/default/264.csrng_err.4130449880/icc_7e55bc60_0e9d174d.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 23, 2024 at 13:10:00 PDT (total: 00:00:03)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:174: simulate] Error 1
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 3 failures:
346.csrng_err.20174445586510119583594198141676266844233476180240083826623521449100370682181
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/346.csrng_err/latest/run.log
UVM_ERROR @ 2798670 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
UVM_INFO @ 2798670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
422.csrng_err.13385436284807274895295945910695805474624251212357134471700628169202162327900
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/422.csrng_err/latest/run.log
UVM_ERROR @ 6303892 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
UVM_INFO @ 6303892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
46.csrng_stress_all.4674312120909344310890380527047020930454255230826099161769453950201720526634
Line 317, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log
UVM_ERROR @ 31168471 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 31168471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1721): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:
111.csrng_intr.64750338474689359332527876627863476735043344538158588124886395252944569970104
Line 308, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/111.csrng_intr/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1721): (time 13391409 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1722): (time 13391409 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1723): (time 13391409 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1724): (time 13391409 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1725): (time 13391409 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed