CSRNG Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	327.564us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	29.296us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	136.557us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	1.444ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	168.824us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	118.687us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	136.557us	20	20	100.00
		csrng_csr_aliasing	8.000s	168.824us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	423.462us	196	200	98.00
V2	alerts	csrng_alert	1.367m	6.390ms	500	500	100.00
V2	err	csrng_err	15.000s	38.669us	496	500	99.20
V2	cmds	csrng_cmds	6.350m	33.516ms	50	50	100.00
V2	life cycle	csrng_cmds	6.350m	33.516ms	50	50	100.00
V2	stress_all	csrng_stress_all	28.933m	49.986ms	47	50	94.00
V2	intr_test	csrng_intr_test	5.000s	211.820us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	40.917us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	20.000s	1.266ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	20.000s	1.266ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	29.296us	5	5	100.00
		csrng_csr_rw	4.000s	136.557us	20	20	100.00
		csrng_csr_aliasing	8.000s	168.824us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	204.548us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	29.296us	5	5	100.00
		csrng_csr_rw	4.000s	136.557us	20	20	100.00
		csrng_csr_aliasing	8.000s	168.824us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	204.548us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	7.000s	107.880us	5	5	100.00
		csrng_tl_intg_err	12.000s	304.603us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	164.269us	50	50	100.00
		csrng_csr_rw	4.000s	136.557us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.367m	6.390ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	28.933m	49.986ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.367m	6.390ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	28.933m	49.986ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.367m	6.390ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	304.603us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
		csrng_sec_cm	7.000s	107.880us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	423.462us	196	200	98.00
		csrng_err	15.000s	38.669us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	11.150m	12.657ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1609	1630	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	98.23	95.85	98.84	96.43	91.90	100.00	97.32	90.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.55898763373365034626051552434091186467175146051846919360998765750561856914809
    Line 298, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3306187931 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3306187931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.83837544910764433467831058118441310772734544511763590880933789439369928970603
    Line 291, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1185081327 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1185081327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

86.csrng_intr.63354870098642337316665058061745454028236618438100155753074334466177968651842
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/86.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 217894922 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 217894922 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 217894922 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 217894922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

122.csrng_intr.18871576112320611312995025473086996497174368128427050977903134136475251858290
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/122.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 54780389 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 54780389 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  54780389 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  54780389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

92.csrng_err.1367851382860465176524211777687955636823658994164334311520534067918224838168
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/92.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  92.csrng_err.3443084824
  
  coverage files:
    model(design data) :  /workspace/coverage/default/92.csrng_err.3443084824/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/92.csrng_err.3443084824/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 24, 2024 at 17:32:22 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

130.csrng_err.110759108663632887503636062051498316845992155382099175505031330619110678529751
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/130.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  130.csrng_err.229574359
  
  coverage files:
    model(design data) :  /workspace/coverage/default/130.csrng_err.229574359/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/130.csrng_err.229574359/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 24, 2024 at 17:32:47 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 1.csrng_stress_all_with_rand_reset.15622476098650501532104474266986306340637910982316359362941625411697767353248
    Line 352, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5301474382 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5301474382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.63447710618987463544331297116301140973064356056985269909363033751211956165104
    Line 335, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8898928000 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8898928000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 12.csrng_stress_all.69541872589696920917946809923538323191308517756723832881033632548236504029385
    Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4410996478 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4410996478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.csrng_stress_all.55100037775526153271787424422999828227904213825445685509940016919712443992854
    Line 341, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 15549805395 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 15549805395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 21.csrng_stress_all.96670282560664275648136522732694706809782723529041854566277539696645091190934
    Line 350, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 16215538046 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 16215538046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```