CSRNG Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	17.709us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	9.000s	109.147us	5	5	100.00
V1	csr_rw	csrng_csr_rw	18.000s	16.445us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	2.017m	10.372ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	17.000s	1.261ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	40.206us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	18.000s	16.445us	20	20	100.00
		csrng_csr_aliasing	17.000s	1.261ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	17.000s	406.123us	195	200	97.50
V2	alerts	csrng_alert	1.233m	5.729ms	500	500	100.00
V2	err	csrng_err	19.000s	22.350us	496	500	99.20
V2	cmds	csrng_cmds	9.750m	50.702ms	50	50	100.00
V2	life cycle	csrng_cmds	9.750m	50.702ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.933m	78.926ms	50	50	100.00
V2	intr_test	csrng_intr_test	12.000s	30.780us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	21.490us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	29.000s	300.636us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	29.000s	300.636us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	9.000s	109.147us	5	5	100.00
		csrng_csr_rw	18.000s	16.445us	20	20	100.00
		csrng_csr_aliasing	17.000s	1.261ms	5	5	100.00
		csrng_same_csr_outstanding	16.000s	47.049us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	9.000s	109.147us	5	5	100.00
		csrng_csr_rw	18.000s	16.445us	20	20	100.00
		csrng_csr_aliasing	17.000s	1.261ms	5	5	100.00
		csrng_same_csr_outstanding	16.000s	47.049us	20	20	100.00
V2		TOTAL			1431	1440	99.38
V2S	tl_intg_err	csrng_sec_cm	11.000s	245.380us	5	5	100.00
		csrng_tl_intg_err	19.000s	137.509us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	111.573us	50	50	100.00
		csrng_csr_rw	18.000s	16.445us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.233m	5.729ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.933m	78.926ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.233m	5.729ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.933m	78.926ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.233m	5.729ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	19.000s	137.509us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
		csrng_sec_cm	11.000s	245.380us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	17.000s	406.123us	195	200	97.50
		csrng_err	19.000s	22.350us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	43.383m	44.254ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1611	1630	98.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	98.26	95.90	98.89	96.43	91.84	100.00	97.32	90.06

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.40720285534529799163092579990672514507613387897650916772678696287429522343135
    Line 299, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2769651303 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2769651303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.79201706450740101106686277748750648060097571154836524017829456282197290711539
    Line 357, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17544799806 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17544799806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

86.csrng_intr.110402494329082103051171501476327534228816790317892353410262404953843173839013
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/86.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 60487625 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 60487625 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  60487625 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  60487625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

141.csrng_intr.1468975693674837116922255218686695672986251596248669770603528428571418404527
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/141.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 14171109 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 14171109 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 14171109 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 14171109 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  14171109 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

255.csrng_err.30277910033601613527420848781565146067437501844310934449429761438003903323311
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/255.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  255.csrng_err.3696745647
  
  coverage files:
    model(design data) :  /workspace/coverage/default/255.csrng_err.3696745647/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/255.csrng_err.3696745647/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 25, 2024 at 16:44:23 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

334.csrng_err.106130937793669211368587731865557900362432270999794455489851730051104146693974
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/334.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  334.csrng_err.2727845718
  
  coverage files:
    model(design data) :  /workspace/coverage/default/334.csrng_err.2727845718/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/334.csrng_err.2727845718/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 25, 2024 at 16:45:15 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 4.csrng_stress_all_with_rand_reset.36482815147846181297529886939535347347205264835114065736248183774529949449558
    Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4715612941 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4715612941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.18503636839701591791578962867617538446358892348799639582992358649856518522956
    Line 283, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 669041086 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 669041086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1767): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

107.csrng_intr.98274414940236661677321283902418845676439658719657536673386569132722869061111
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/107.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 26692841 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 26692841 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 26692841 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 26692841 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 26692841 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed