CSRNG Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	19.000s	22.008us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	46.299us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	210.027us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	34.000s	1.560ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	379.290us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	11.000s	66.776us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	210.027us	20	20	100.00
		csrng_csr_aliasing	10.000s	379.290us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	114.467us	196	200	98.00
V2	alerts	csrng_alert	1.633m	8.128ms	500	500	100.00
V2	err	csrng_err	24.000s	20.704us	496	500	99.20
V2	cmds	csrng_cmds	11.717m	64.403ms	49	50	98.00
V2	life cycle	csrng_cmds	11.717m	64.403ms	49	50	98.00
V2	stress_all	csrng_stress_all	25.667m	107.277ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	49.384us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	83.633us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	437.196us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	437.196us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	46.299us	5	5	100.00
		csrng_csr_rw	5.000s	210.027us	20	20	100.00
		csrng_csr_aliasing	10.000s	379.290us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	60.298us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	46.299us	5	5	100.00
		csrng_csr_rw	5.000s	210.027us	20	20	100.00
		csrng_csr_aliasing	10.000s	379.290us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	60.298us	20	20	100.00
V2		TOTAL			1430	1440	99.31
V2S	tl_intg_err	csrng_sec_cm	7.000s	83.003us	5	5	100.00
		csrng_tl_intg_err	13.000s	240.950us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	68.115us	50	50	100.00
		csrng_csr_rw	5.000s	210.027us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.633m	8.128ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.667m	107.277ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.633m	8.128ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.667m	107.277ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.633m	8.128ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	240.950us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
		csrng_sec_cm	7.000s	83.003us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	114.467us	196	200	98.00
		csrng_err	24.000s	20.704us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.261h	595.030ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1610	1630	98.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	98.26	95.90	98.89	96.48	91.84	100.00	97.14	90.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 0.csrng_stress_all_with_rand_reset.101193533219693989501615318152664276549243243002003024924859910395030110697703
    Line 282, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 161617482 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 161617482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.74661647476099366205109318122582027336392172651373302632060557548624791821631
    Line 302, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4249717241 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4249717241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:829) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 1.csrng_stress_all_with_rand_reset.45651686474857238459156705487367390720530179440744019035617750351387637753433
    Line 392, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 96802330324 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 96802330324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.10851933943941608681109468415205636982198166089820283467015437285810278817345
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24214842581 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 24214842581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

10.csrng_intr.46027230898759824620838685443667474890308727529913687616873173060280312761348
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 56629148 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 56629148 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  56629148 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  56629148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

137.csrng_intr.10179341984499184506499189272688539158577883568196289617885729998225746703395
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/137.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 20223020 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 20223020 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  20223020 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  20223020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

88.csrng_err.12883690632232035763302517362028412330903419222738963859905748875694646399065
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/88.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  88.csrng_err.3065417817
  
  coverage files:
    model(design data) :  /workspace/coverage/default/88.csrng_err.3065417817/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/88.csrng_err.3065417817/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 26, 2024 at 16:25:30 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

197.csrng_err.105851169399405083902055688139792459765462794768417596597921081657446358847747
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/197.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  197.csrng_err.3915387139
  
  coverage files:
    model(design data) :  /workspace/coverage/default/197.csrng_err.3915387139/icc_57048ec4_251369e9.ucm
    data               :  /workspace/coverage/default/197.csrng_err.3915387139/icc_57048ec4_251369e9.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jun 26, 2024 at 16:26:14 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 9.csrng_stress_all.78062942260657245806727227334704766755250209598085239054189673231007541989602
    Line 340, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 15223927349 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 15223927349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 27.csrng_cmds.88042736978510075517230098067723795892832331593378010312028087396975707230557
    Line 406, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 1710745657 ps: (csrng_env_cfg.sv:287) [cfg] Check failed hw_reseed_counter == reseed_counter[app] (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 1710745657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```