CSRNG Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	60.848us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	38.562us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	51.019us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	35.000s	2.365ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	526.069us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	28.947us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	51.019us	20	20	100.00
		csrng_csr_aliasing	8.000s	526.069us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	85.155us	197	200	98.50
V2	alerts	csrng_alert	1.033m	5.059ms	500	500	100.00
V2	err	csrng_err	19.000s	35.918us	499	500	99.80
V2	cmds	csrng_cmds	13.933m	74.591ms	49	50	98.00
V2	life cycle	csrng_cmds	13.933m	74.591ms	49	50	98.00
V2	stress_all	csrng_stress_all	25.083m	56.799ms	49	50	98.00
V2	intr_test	csrng_intr_test	14.000s	21.625us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	23.335us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	32.000s	2.604ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	32.000s	2.604ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	38.562us	5	5	100.00
		csrng_csr_rw	5.000s	51.019us	20	20	100.00
		csrng_csr_aliasing	8.000s	526.069us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	71.345us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	38.562us	5	5	100.00
		csrng_csr_rw	5.000s	51.019us	20	20	100.00
		csrng_csr_aliasing	8.000s	526.069us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	71.345us	20	20	100.00
V2		TOTAL			1434	1440	99.58
V2S	tl_intg_err	csrng_sec_cm	17.000s	519.909us	5	5	100.00
		csrng_tl_intg_err	25.000s	502.116us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	28.594us	50	50	100.00
		csrng_csr_rw	5.000s	51.019us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.033m	5.059ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.083m	56.799ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.033m	5.059ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.083m	56.799ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.033m	5.059ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	25.000s	502.116us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
		csrng_sec_cm	17.000s	519.909us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	85.155us	197	200	98.50
		csrng_err	19.000s	35.918us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.037h	94.676ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1614	1630	99.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	98.26	95.90	98.89	96.43	91.84	100.00	97.32	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 1.csrng_stress_all_with_rand_reset.63253568302250274712956636420319941742958947911849206133324670695858828142206
    Line 633, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 94675540111 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 94675540111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.92140467983593878832825793352305914573430178668159778774450541612034250942497
    Line 335, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13780555844 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13780555844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

10.csrng_intr.53550073572236714556470252550299575687731358742287563510304810473922959306684
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 14111540 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 14111540 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 14111540 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 14111540 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  14111540 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

95.csrng_intr.70498888149910862595335064313887081842463904504150644179765337189640736936103
Line 310, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/95.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 42318047 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 42318047 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  42318047 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  42318047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 0.csrng_stress_all_with_rand_reset.18068065750625707527168109501876714591392088308843240600726584393845793908867
    Line 392, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10029429311 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10029429311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:163) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 46.csrng_stress_all.52881966388238208158106056583938941065729694615806189668107731706684690190103
    Line 348, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 38445677423 ps: (csrng_scoreboard.sv:163) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 38445677423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:288) [scoreboard] Check failed cmd_sts[SW_APP] == item.d_data[*:*] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 49.csrng_cmds.72781656932085327869636328708682103981016413416143816954625595507859596550655
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/49.csrng_cmds/latest/run.log
```
  UVM_ERROR @ 248420256 ps: (csrng_scoreboard.sv:288) [uvm_test_top.env.scoreboard] Check failed cmd_sts[SW_APP] == item.d_data[5:3] (3 [0x3] vs 0 [0x0])
  UVM_INFO @ 248420256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

184.csrng_err.1158029158641682147709951860013952207564987686632852309088544839138209971012
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/184.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  184.csrng_err.2453420868
  
  coverage files:
    model(design data) :  /workspace/coverage/default/184.csrng_err.2453420868/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/184.csrng_err.2453420868/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 07, 2024 at 16:28:30 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:187: simulate] Error 1