CSRNG Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	103.255us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	99.251us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	88.363us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	48.000s	2.178ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	716.409us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	138.250us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	88.363us	20	20	100.00
		csrng_csr_aliasing	11.000s	716.409us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	29.090us	197	200	98.50
V2	alerts	csrng_alert	1.117m	4.365ms	500	500	100.00
V2	err	csrng_err	14.000s	20.539us	493	500	98.60
V2	cmds	csrng_cmds	8.367m	32.039ms	50	50	100.00
V2	life cycle	csrng_cmds	8.367m	32.039ms	50	50	100.00
V2	stress_all	csrng_stress_all	20.500m	32.629ms	49	50	98.00
V2	intr_test	csrng_intr_test	4.000s	49.820us	50	50	100.00
V2	alert_test	csrng_alert_test	19.000s	232.285us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	1.396ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	1.396ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	99.251us	5	5	100.00
		csrng_csr_rw	4.000s	88.363us	20	20	100.00
		csrng_csr_aliasing	11.000s	716.409us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	301.335us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	99.251us	5	5	100.00
		csrng_csr_rw	4.000s	88.363us	20	20	100.00
		csrng_csr_aliasing	11.000s	716.409us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	301.335us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	6.000s	266.204us	5	5	100.00
		csrng_tl_intg_err	19.000s	1.422ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	14.235us	50	50	100.00
		csrng_csr_rw	4.000s	88.363us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.117m	4.365ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	20.500m	32.629ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.117m	4.365ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	20.500m	32.629ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.117m	4.365ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	19.000s	1.422ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
		csrng_sec_cm	6.000s	266.204us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	29.090us	197	200	98.50
		csrng_err	14.000s	20.539us	493	500	98.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	50.267m	56.524ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1609	1630	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	98.23	95.85	98.86	96.54	91.84	100.00	97.32	90.74

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.95384762832201510275991383218528405363505107294307048762629228942345336076257
    Line 379, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20594475299 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20594475299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.24083657859402475665140375777584516580625587148523449462328054012043856553474
    Line 334, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8447063723 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8447063723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 6 failures:

Test csrng_err has 6 failures.

10.csrng_err.48269695172655200607044791895182054718655531243045069272886860491128259851619
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  10.csrng_err.191214947
  
  coverage files:
    model(design data) :  /workspace/coverage/default/10.csrng_err.191214947/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/10.csrng_err.191214947/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 20, 2024 at 17:47:54 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

73.csrng_err.76928696816860301617395093442514152914616025034356924570285975810414976203021
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/73.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  73.csrng_err.1197242637
  
  coverage files:
    model(design data) :  /workspace/coverage/default/73.csrng_err.1197242637/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/73.csrng_err.1197242637/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 20, 2024 at 17:48:39 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 3.csrng_stress_all_with_rand_reset.20005925865594541288688287368320115851019436824159069082369859132866574976251
    Line 366, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14200810800 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14200810800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.64419748734463376488789550072035351796878710183674812430831994715189152470787
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14915528657 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14915528657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

122.csrng_intr.541357160231750940192710721139181234176551669632351643100433362347310092372
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/122.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 62659061 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 62659061 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  62659061 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  62659061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

169.csrng_intr.18968105484688783877451951865910243093024103193670497447471298822299167171538
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/169.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 31150281 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 31150281 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  31150281 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  31150281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 0.csrng_stress_all.76248958515043597180758092074981968588097927416636237533684698826511445354134
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 151299432 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 151299432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 58.csrng_err.38954173904760279953296842765364659120474152273457221807163309833541419661794
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/58.csrng_err/latest/run.log
```
  UVM_ERROR @   3518460 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   3518460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1767): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

168.csrng_intr.67895281431708846717096632437006575265537721524692713825623981512667872661283
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/168.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 12815461 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 12815461 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 12815461 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 12815461 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 12815461 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed