CSRNG Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	15.000s	147.309us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	35.229us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	190.111us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.267m	5.712ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	69.837us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	62.822us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	190.111us	20	20	100.00
		csrng_csr_aliasing	6.000s	69.837us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	48.140us	196	200	98.00
V2	alerts	csrng_alert	51.000s	3.647ms	500	500	100.00
V2	err	csrng_err	18.000s	65.842us	494	500	98.80
V2	cmds	csrng_cmds	9.383m	45.696ms	48	50	96.00
V2	life cycle	csrng_cmds	9.383m	45.696ms	48	50	96.00
V2	stress_all	csrng_stress_all	42.183m	189.130ms	50	50	100.00
V2	intr_test	csrng_intr_test	4.000s	16.267us	50	50	100.00
V2	alert_test	csrng_alert_test	16.000s	276.242us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	25.000s	1.989ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	25.000s	1.989ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	35.229us	5	5	100.00
		csrng_csr_rw	5.000s	190.111us	20	20	100.00
		csrng_csr_aliasing	6.000s	69.837us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	102.258us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	35.229us	5	5	100.00
		csrng_csr_rw	5.000s	190.111us	20	20	100.00
		csrng_csr_aliasing	6.000s	69.837us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	102.258us	20	20	100.00
V2		TOTAL			1428	1440	99.17
V2S	tl_intg_err	csrng_sec_cm	8.000s	220.831us	5	5	100.00
		csrng_tl_intg_err	16.000s	1.146ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	176.400us	50	50	100.00
		csrng_csr_rw	5.000s	190.111us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	51.000s	3.647ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	42.183m	189.130ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	51.000s	3.647ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	42.183m	189.130ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	51.000s	3.647ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	1.146ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
		csrng_sec_cm	8.000s	220.831us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	48.140us	196	200	98.00
		csrng_err	18.000s	65.842us	494	500	98.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	21.950m	51.151ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1608	1630	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	98.26	95.90	98.89	96.65	91.84	100.00	97.32	90.53

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.84703524661144415672232553193875253881019909171110649875803514148346214414736
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12600661320 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12600661320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.62579982841577724282028580276355985787759891656372051812862805286479726830185
    Line 358, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20818199403 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20818199403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 6 failures:

Test csrng_err has 6 failures.

8.csrng_err.102961878853530505868040067988074324801699480407530953061435942248899318554174
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  8.csrng_err.2582552126
  
  coverage files:
    model(design data) :  /workspace/coverage/default/8.csrng_err.2582552126/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/8.csrng_err.2582552126/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 16, 2024 at 16:45:58 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

82.csrng_err.71199758959086945934769568861390433348153015522137573124591956923337492969598
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/82.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  82.csrng_err.3806902398
  
  coverage files:
    model(design data) :  /workspace/coverage/default/82.csrng_err.3806902398/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/82.csrng_err.3806902398/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 16, 2024 at 16:46:51 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

9.csrng_intr.27378244833427649080170029103486154968572251333515438179546614224134351005291
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 31737112 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 31737112 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  31737112 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  31737112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.csrng_intr.101110593249530055468075512173529912668496496808663638805289670212778849411659
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 20974993 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 20974993 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  20974993 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  20974993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 3.csrng_stress_all_with_rand_reset.71323512752404690388477986076782836091188783066451232827550715485954671762638
    Line 479, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51150808588 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 51150808588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all_with_rand_reset.31848713776107777899482261678150395327576026047271656345124157319491081472833
    Line 371, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18165811796 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18165811796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:306) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 2 failures:
- Test csrng_cmds has 2 failures.
  - 9.csrng_cmds.64093805669873943039005052269314517053255213962672649335096102989541336359485
    Line 411, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 17033856462 ps: (csrng_env_cfg.sv:306) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 17033856462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.csrng_cmds.106940027465091820255861045271427429675002336778846258550072543520383211695593
    Line 411, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 2621782359 ps: (csrng_env_cfg.sv:306) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2621782359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```