CSRNG Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	27.317us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	19.092us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	55.117us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	38.000s	1.787ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	209.573us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	352.842us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	55.117us	20	20	100.00
		csrng_csr_aliasing	9.000s	209.573us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	11.000s	176.216us	198	200	99.00
V2	alerts	csrng_alert	1.083m	4.721ms	500	500	100.00
V2	err	csrng_err	15.000s	40.360us	495	500	99.00
V2	cmds	csrng_cmds	6.450m	16.590ms	48	50	96.00
V2	life cycle	csrng_cmds	6.450m	16.590ms	48	50	96.00
V2	stress_all	csrng_stress_all	35.133m	144.393ms	46	50	92.00
V2	intr_test	csrng_intr_test	6.000s	129.822us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	26.550us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	718.515us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	718.515us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	19.092us	5	5	100.00
		csrng_csr_rw	8.000s	55.117us	20	20	100.00
		csrng_csr_aliasing	9.000s	209.573us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	37.095us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	19.092us	5	5	100.00
		csrng_csr_rw	8.000s	55.117us	20	20	100.00
		csrng_csr_aliasing	9.000s	209.573us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	37.095us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	7.000s	292.507us	5	5	100.00
		csrng_tl_intg_err	17.000s	395.255us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	10.000s	39.767us	50	50	100.00
		csrng_csr_rw	8.000s	55.117us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	4.721ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	35.133m	144.393ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	4.721ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	35.133m	144.393ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	4.721ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	395.255us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
		csrng_sec_cm	7.000s	292.507us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	11.000s	176.216us	198	200	99.00
		csrng_err	15.000s	40.360us	495	500	99.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	35.317m	39.839ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1607	1630	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	98.23	95.85	98.86	96.59	91.84	100.00	97.14	90.63

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 1.csrng_stress_all_with_rand_reset.48638842074945116847137810615138435905127463740331613911881620708698149576557
    Line 338, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26588429397 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26588429397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.33572923731537094557815276769718153585013184447810473143951351651427566457578
    Line 470, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39838942699 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 39838942699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 0.csrng_stress_all_with_rand_reset.11314880612673134273656753095316236231847848179434965894799907685961752463635
    Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4157299627 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4157299627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.31043867718043533048715631539224324858407233009188266894286725479049692797294
    Line 417, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14031731834 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14031731834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

24.csrng_err.29410243077771468686949879062002240497075382567842206471368754467314676992666
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  24.csrng_err.337054362
  
  coverage files:
    model(design data) :  /workspace/coverage/default/24.csrng_err.337054362/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/24.csrng_err.337054362/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 17, 2024 at 16:29:37 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

143.csrng_err.39326532022879058895453720650491029540754382516074250971758741161739124229114
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/143.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  143.csrng_err.445924346
  
  coverage files:
    model(design data) :  /workspace/coverage/default/143.csrng_err.445924346/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/143.csrng_err.445924346/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 17, 2024 at 16:30:45 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 10.csrng_stress_all.90269365249210136550934531170513322074130853989073338993710413339407253601167
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 7630034404 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 7630034404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.csrng_stress_all.93641794490898019481038676042659167990560387372238310344541177552020822971341
    Line 351, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1528562560 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1528562560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

66.csrng_intr.61567389837150408525566559488952223279895194569030459187388062726702849139039
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/66.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 16835591 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 16835591 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  16835591 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  16835591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

126.csrng_intr.25037225944141142333847260452408932850834975164162734789394653980127672354382
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/126.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 20883466 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 20883466 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 20883466 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 20883466 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  20883466 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

UVM_FATAL (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 9.csrng_cmds.101811451864505510653502386059932414401275419091275195627469035483418092338157
    Line 401, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 999024306 ps: (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (283742466179017771961301985768714311623 [0xd576cfab8392a893a88a223c2ab497c7] vs 0 [0x0])
  UVM_INFO @ 999024306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csrng_env_cfg.sv:306) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 18.csrng_cmds.28148102527416663240391669524380521056376650709927362493490847760208483308402
    Line 411, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 2626699654 ps: (csrng_env_cfg.sv:306) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 2626699654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 40.csrng_stress_all.4018794644793834406635247177455931292836293996683942807653651415323139041549
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/40.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  11848237 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  11848237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 295.csrng_err.111324828139013002124720260836629545902916687431861805376193292878235094855770
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/295.csrng_err/latest/run.log
```
  UVM_ERROR @  15615273 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  15615273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```