CSRNG Simulation Results

Sunday July 14 2024 23:02:31 UTC

GitHub Revision: `c04cc5d074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 63544391231451201456762274895161998707503467555380647510071702152169450996489

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	335.126us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	69.019us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	36.851us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	44.000s	2.174ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	554.217us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	120.199us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	36.851us	20	20	100.00
		csrng_csr_aliasing	11.000s	554.217us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	8.000s	470.336us	198	200	99.00
V2	alerts	csrng_alert	1.067m	5.140ms	500	500	100.00
V2	err	csrng_err	5.000s	20.339us	493	500	98.60
V2	cmds	csrng_cmds	14.900m	77.725ms	46	50	92.00
V2	life cycle	csrng_cmds	14.900m	77.725ms	46	50	92.00
V2	stress_all	csrng_stress_all	38.083m	201.482ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	47.141us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	94.606us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	664.373us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	664.373us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	69.019us	5	5	100.00
		csrng_csr_rw	4.000s	36.851us	20	20	100.00
		csrng_csr_aliasing	11.000s	554.217us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	401.177us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	69.019us	5	5	100.00
		csrng_csr_rw	4.000s	36.851us	20	20	100.00
		csrng_csr_aliasing	11.000s	554.217us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	401.177us	20	20	100.00
V2		TOTAL			1425	1440	98.96
V2S	tl_intg_err	csrng_sec_cm	6.000s	122.732us	5	5	100.00
		csrng_tl_intg_err	20.000s	1.732ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	32.795us	50	50	100.00
		csrng_csr_rw	4.000s	36.851us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.067m	5.140ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	38.083m	201.482ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.067m	5.140ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	38.083m	201.482ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.067m	5.140ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	20.000s	1.732ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
		csrng_sec_cm	6.000s	122.732us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	8.000s	470.336us	198	200	99.00
		csrng_err	5.000s	20.339us	493	500	98.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	23.817m	14.995ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1605	1630	98.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	98.23	95.85	98.86	96.59	91.84	100.00	97.14	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.77672120859080423835854460284535879189024434752841287141735631965650749247127
    Line 301, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4774998506 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4774998506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.76179328726562523250240096991687477008063581699115143990646009665950274874822
    Line 344, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9200407151 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9200407151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 6 failures:

Test csrng_err has 6 failures.

6.csrng_err.48944383603266271017577215973301150145097411291270793953555785088419049899740
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  6.csrng_err.3207202524
  
  coverage files:
    model(design data) :  /workspace/coverage/default/6.csrng_err.3207202524/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/6.csrng_err.3207202524/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 14, 2024 at 18:25:58 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

192.csrng_err.47878016428410528973364540472846396171607583186835535996171427661977988400840
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/192.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  192.csrng_err.1060931272
  
  coverage files:
    model(design data) :  /workspace/coverage/default/192.csrng_err.1060931272/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/192.csrng_err.1060931272/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 14, 2024 at 18:28:43 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 4 more failures.

UVM_FATAL (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 4 failures:

Test csrng_cmds has 4 failures.

0.csrng_cmds.50489575965712028170017078169013593681632376330032876941033645029336088998707
Line 391, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_cmds/latest/run.log

  UVM_FATAL @ 16850851803 ps: (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (304587933513181674397342018798680815919 [0xe525808f35ae7bf1e68d8790be34392f] vs 0 [0x0])
  UVM_INFO @ 16850851803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.csrng_cmds.59831016510143583940289202795671076981329170814184819735615316395051173498883
Line 401, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_cmds/latest/run.log

  UVM_FATAL @ 1797939043 ps: (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (23614766090489105595734268029088556789 [0x11c409dc135b3eb3b5ef9d41c9cbe6f5] vs 0 [0x0])
  UVM_INFO @ 1797939043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 1.csrng_stress_all_with_rand_reset.77907562447061455205793942054941741517034144833863255413146919695426369348740
    Line 408, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16767457341 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16767457341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.114556836336026939428324966598167694534699421338213654897676976788751542904726
    Line 466, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14994854801 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14994854801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

28.csrng_intr.84637210883574972905710251734382662831211666801240910749602454127274924804245
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 55397773 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 55397773 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  55397773 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  55397773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

139.csrng_intr.91791142274869941299978607911493375940501186149696400342337310380195473855999
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/139.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 10986953 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 10986953 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  10986953 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  10986953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 6.csrng_stress_all.46703365105977688354496845249520218615966401313567445050056820773489807901112
    Line 340, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 30428317491 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 30428317491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 7.csrng_stress_all.107937968951152479247705563293948695383753706390947048175698463436838526028512
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  44589839 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  44589839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 386.csrng_err.61729749686306721781732239958303828177473348456631720378591520216111567461195
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/386.csrng_err/latest/run.log
```
  UVM_ERROR @  14222774 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  14222774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```