CSRNG Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	334.803us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	20.867us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	189.067us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.300m	6.935ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	501.558us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	410.926us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	189.067us	20	20	100.00
		csrng_csr_aliasing	10.000s	501.558us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	391.628us	194	200	97.00
V2	alerts	csrng_alert	1.083m	4.257ms	500	500	100.00
V2	err	csrng_err	17.000s	32.915us	496	500	99.20
V2	cmds	csrng_cmds	5.017m	21.224ms	50	50	100.00
V2	life cycle	csrng_cmds	5.017m	21.224ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.083m	122.138ms	48	50	96.00
V2	intr_test	csrng_intr_test	5.000s	190.875us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	30.406us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	462.780us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	462.780us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	20.867us	5	5	100.00
		csrng_csr_rw	5.000s	189.067us	20	20	100.00
		csrng_csr_aliasing	10.000s	501.558us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	286.928us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	20.867us	5	5	100.00
		csrng_csr_rw	5.000s	189.067us	20	20	100.00
		csrng_csr_aliasing	10.000s	501.558us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	286.928us	20	20	100.00
V2		TOTAL			1428	1440	99.17
V2S	tl_intg_err	csrng_sec_cm	6.000s	78.324us	5	5	100.00
		csrng_tl_intg_err	11.000s	446.159us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	37.930us	50	50	100.00
		csrng_csr_rw	5.000s	189.067us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	4.257ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.083m	122.138ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	4.257ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.083m	122.138ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	4.257ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	446.159us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
		csrng_sec_cm	6.000s	78.324us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	391.628us	194	200	97.00
		csrng_err	17.000s	32.915us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	43.917m	26.201ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1608	1630	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.05	98.17	95.69	98.76	96.54	91.71	100.00	96.60	90.42

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.81920894231251552037312162910852881192340028936246858644983429142034099721193
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10619189436 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10619189436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.81255133726913789772954616034104674102867525185976164332705977195711299799787
    Line 376, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 31997088064 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 31997088064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 6 failures:

Test csrng_intr has 6 failures.

17.csrng_intr.108997699305071359512626779140988596750694428177421282039114376244311279353799
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 22704472 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 22704472 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  22704472 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  22704472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

52.csrng_intr.53926929047784784696973549591584794860957118727776987502323843664235403688540
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/52.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 57288982 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 57288982 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  57288982 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  57288982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 1.csrng_stress_all_with_rand_reset.28090291226157532587502653043611020859023968289162142115522661801495214820221
    Line 610, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26201416688 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26201416688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.33677109924973867546323135098012241441025888254012082672764901855991167133866
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 220824567 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 220824567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

131.csrng_err.69720604159901231754359702798979260161991639982409743676496844186488897909733
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/131.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  131.csrng_err.842118117
  
  coverage files:
    model(design data) :  /workspace/coverage/default/131.csrng_err.842118117/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/131.csrng_err.842118117/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 18, 2024 at 17:24:56 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

204.csrng_err.65621990605873552627999606512494417589634994294604406884139707492618457520225
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/204.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  204.csrng_err.2519406689
  
  coverage files:
    model(design data) :  /workspace/coverage/default/204.csrng_err.2519406689/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/204.csrng_err.2519406689/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 18, 2024 at 17:52:22 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 23.csrng_stress_all.103104933381034568515266138902657135061871419762143860158356926317498963419889
    Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 146906085 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 146906085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.csrng_stress_all.107353142261192960848176576330066698533383597191253333366268244701007269536029
    Line 328, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/29.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 14667836368 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 14667836368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 359.csrng_err.109645477218584642594854251698552784316512020937238177820458852410131906605291
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/359.csrng_err/latest/run.log
```
  UVM_ERROR @   6284074 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   6284074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```