CSRNG Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	77.719us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	19.811us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	14.721us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	45.000s	2.082ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	135.455us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	134.432us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	14.721us	20	20	100.00
		csrng_csr_aliasing	6.000s	135.455us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	8.000s	435.552us	197	200	98.50
V2	alerts	csrng_alert	59.000s	4.261ms	500	500	100.00
V2	err	csrng_err	5.000s	23.650us	498	500	99.60
V2	cmds	csrng_cmds	10.383m	48.084ms	49	50	98.00
V2	life cycle	csrng_cmds	10.383m	48.084ms	49	50	98.00
V2	stress_all	csrng_stress_all	17.200m	38.704ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	31.741us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	69.828us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	550.412us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	550.412us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	19.811us	5	5	100.00
		csrng_csr_rw	4.000s	14.721us	20	20	100.00
		csrng_csr_aliasing	6.000s	135.455us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	565.056us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	19.811us	5	5	100.00
		csrng_csr_rw	4.000s	14.721us	20	20	100.00
		csrng_csr_aliasing	6.000s	135.455us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	565.056us	20	20	100.00
V2		TOTAL			1432	1440	99.44
V2S	tl_intg_err	csrng_sec_cm	7.000s	103.454us	5	5	100.00
		csrng_tl_intg_err	21.000s	1.547ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	161.342us	50	50	100.00
		csrng_csr_rw	4.000s	14.721us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	59.000s	4.261ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	17.200m	38.704ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	59.000s	4.261ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	17.200m	38.704ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	59.000s	4.261ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	21.000s	1.547ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
		csrng_sec_cm	7.000s	103.454us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	8.000s	435.552us	197	200	98.50
		csrng_err	5.000s	23.650us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	30.917m	152.670ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1612	1630	98.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	98.26	95.90	98.89	96.59	91.84	100.00	97.32	90.42

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 1.csrng_stress_all_with_rand_reset.114792468766398309840875558176986182858698108585241828706492346722413543498956
    Line 287, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2426999717 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2426999717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.31837321856342275625602379178861947006216430301250659622322026900329134179365
    Line 333, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 152669691636 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 152669691636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:826) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 0.csrng_stress_all_with_rand_reset.79998926999155244760164526629446908396129676172981622362580916655166317186117
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3145015368 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3145015368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.60440992387842320507797120842952970427962371581083210439834974165735706378706
    Line 297, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2196631542 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2196631542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

14.csrng_intr.43414906978694263781317300555564609229569680956583155619991020618653710843370
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 61700835 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 61700835 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  61700835 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  61700835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

92.csrng_intr.70165740377189543432676709592486907256252001711202288236382660758508513714478
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/92.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 131536385 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 131536385 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 131536385 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 131536385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

4.csrng_stress_all.20892578276970534146895364065691342312117974339220642511074216653954219503982
Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all/latest/run.log

  UVM_ERROR @ 11300157202 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 11300157202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.csrng_stress_all.103711366613146354837946700570347364176264859355211637210276591746134560621924
Line 357, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log

  UVM_ERROR @ 10180408830 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 10180408830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

91.csrng_err.96757573580949407515303333010167289115784131552200103341915491534635420849093
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/91.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  91.csrng_err.1738249157
  
  coverage files:
    model(design data) :  /workspace/coverage/default/91.csrng_err.1738249157/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/91.csrng_err.1738249157/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 15, 2024 at 17:43:16 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

277.csrng_err.41334573358927732422979533831276489080545841948278747298610470654166093038807
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/277.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  277.csrng_err.730891479
  
  coverage files:
    model(design data) :  /workspace/coverage/default/277.csrng_err.730891479/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/277.csrng_err.730891479/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 15, 2024 at 17:45:19 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

UVM_FATAL (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (* [*] vs * [*]) has 1 failures:
- Test csrng_cmds has 1 failures.
  - 28.csrng_cmds.104425100263969799231387270062553639285245037669215103802709758506113621612922
    Line 391, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/28.csrng_cmds/latest/run.log
```
  UVM_FATAL @ 2602160287 ps: (csrng_env_cfg.sv:310) [cfg] Check failed hw_v == v[app] (10900486334819864862112341302659867570 [0x8335b78476a340e0835a6bd105d63b2] vs 0 [0x0])
  UVM_INFO @ 2602160287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```