CSRNG Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	18.489us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	101.497us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	74.045us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	48.000s	2.165ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	49.845us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	57.368us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	74.045us	20	20	100.00
		csrng_csr_aliasing	6.000s	49.845us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	91.788us	196	200	98.00
V2	alerts	csrng_alert	49.000s	2.892ms	500	500	100.00
V2	err	csrng_err	14.000s	25.630us	495	500	99.00
V2	cmds	csrng_cmds	6.617m	29.611ms	50	50	100.00
V2	life cycle	csrng_cmds	6.617m	29.611ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.767m	121.721ms	48	50	96.00
V2	intr_test	csrng_intr_test	6.000s	241.103us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	71.912us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	16.000s	782.895us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	16.000s	782.895us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	101.497us	5	5	100.00
		csrng_csr_rw	4.000s	74.045us	20	20	100.00
		csrng_csr_aliasing	6.000s	49.845us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	169.453us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	101.497us	5	5	100.00
		csrng_csr_rw	4.000s	74.045us	20	20	100.00
		csrng_csr_aliasing	6.000s	49.845us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	169.453us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	11.000s	258.167us	5	5	100.00
		csrng_tl_intg_err	15.000s	1.001ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	32.244us	50	50	100.00
		csrng_csr_rw	4.000s	74.045us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	49.000s	2.892ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.767m	121.721ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	49.000s	2.892ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.767m	121.721ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	49.000s	2.892ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	1.001ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
		csrng_sec_cm	11.000s	258.167us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	91.788us	196	200	98.00
		csrng_err	14.000s	25.630us	495	500	99.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	29.167m	23.682ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1609	1630	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	98.23	95.85	98.86	96.54	91.90	100.00	97.32	90.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 1.csrng_stress_all_with_rand_reset.105141874163069433549402656749998982731020656872187953591749853887801154742717
    Line 358, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5956164871 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5956164871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.57801349851589070824225939821637166940668710923298745047209658730708765907186
    Line 469, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23681646358 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23681646358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 0.csrng_stress_all_with_rand_reset.672692206884290048594237889888459626523469965943943707100328101362189113017
    Line 291, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 750527474 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 750527474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.12269640385841237731556168385536779373113286604380618438185068419931965583575
    Line 346, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9992305638 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9992305638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

56.csrng_err.76240802780913933330700587878296101817942412686619267142672714866567513023515
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/56.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  56.csrng_err.1353360411
  
  coverage files:
    model(design data) :  /workspace/coverage/default/56.csrng_err.1353360411/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/56.csrng_err.1353360411/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 21, 2024 at 16:42:13 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

97.csrng_err.1560662863639363303282319872271611189855641263883204830902013078512416637738
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/97.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  97.csrng_err.1340130090
  
  coverage files:
    model(design data) :  /workspace/coverage/default/97.csrng_err.1340130090/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/97.csrng_err.1340130090/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 21, 2024 at 16:42:24 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

95.csrng_intr.111821281369329952064863071155121027500863415185547442967640218404531830386862
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/95.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 19474381 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 19474381 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  19474381 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  19474381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

114.csrng_intr.57619650584426320744934417659626985091742978834808787425058820656366671751329
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/114.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 35635796 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 35635796 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  35635796 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  35635796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 4.csrng_stress_all.11792387579112021512407361864384916277681999649311110277965018788738580007992
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4770569995 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4770569995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.csrng_stress_all.59514141449233552454091382472073081303480385759003721609373959007126792147021
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 120866388 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 120866388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 164.csrng_err.1489532425372620036472537066438161481478956375565393213293150232137386158620
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/164.csrng_err/latest/run.log
```
  UVM_ERROR @  15828548 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  15828548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```