CSRNG Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	234.797us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	8.000s	15.832us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	21.827us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	47.000s	2.264ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	637.411us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	127.020us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	21.827us	20	20	100.00
		csrng_csr_aliasing	12.000s	637.411us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	36.875us	197	200	98.50
V2	alerts	csrng_alert	50.000s	3.900ms	500	500	100.00
V2	err	csrng_err	17.000s	20.812us	494	500	98.80
V2	cmds	csrng_cmds	6.500m	18.201ms	49	50	98.00
V2	life cycle	csrng_cmds	6.500m	18.201ms	49	50	98.00
V2	stress_all	csrng_stress_all	32.133m	145.749ms	44	50	88.00
V2	intr_test	csrng_intr_test	14.000s	40.121us	50	50	100.00
V2	alert_test	csrng_alert_test	26.000s	61.322us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	18.000s	829.533us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	18.000s	829.533us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	8.000s	15.832us	5	5	100.00
		csrng_csr_rw	5.000s	21.827us	20	20	100.00
		csrng_csr_aliasing	12.000s	637.411us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	328.378us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	8.000s	15.832us	5	5	100.00
		csrng_csr_rw	5.000s	21.827us	20	20	100.00
		csrng_csr_aliasing	12.000s	637.411us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	328.378us	20	20	100.00
V2		TOTAL			1424	1440	98.89
V2S	tl_intg_err	csrng_sec_cm	8.000s	203.880us	5	5	100.00
		csrng_tl_intg_err	23.000s	677.891us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	10.000s	47.802us	50	50	100.00
		csrng_csr_rw	5.000s	21.827us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	50.000s	3.900ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.133m	145.749ms	44	50	88.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	50.000s	3.900ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.133m	145.749ms	44	50	88.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	50.000s	3.900ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	23.000s	677.891us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
		csrng_sec_cm	8.000s	203.880us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	36.875us	197	200	98.50
		csrng_err	17.000s	20.812us	494	500	98.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	28.217m	90.443ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1604	1630	98.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	5	55.56
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	98.23	95.85	98.86	96.54	91.90	100.00	97.32	90.42

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.23821001347416825970528174712601858669513166973536591860272214010844493863142
    Line 362, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67784621636 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 67784621636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.74566358929665257634480381446995120034315845925700152521254042727846791561829
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108011932 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 108011932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:

Test csrng_err has 5 failures.

259.csrng_err.65518756172368683568656557714355742242840434884298450474077508874054595164647
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/259.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  259.csrng_err.1256372711
  
  coverage files:
    model(design data) :  /workspace/coverage/default/259.csrng_err.1256372711/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/259.csrng_err.1256372711/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 22, 2024 at 17:54:48 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

290.csrng_err.99707069057811701409758495086332242457066484240559134291621774604184677795368
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/290.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  290.csrng_err.3769910824
  
  coverage files:
    model(design data) :  /workspace/coverage/default/290.csrng_err.3769910824/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/290.csrng_err.3769910824/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 22, 2024 at 17:55:02 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 2.csrng_stress_all_with_rand_reset.32114844997373976082520837902099125907896704784909494589605956107620562518712
    Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2973620119 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2973620119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.93709075165435813546959837861967130759901531661112509843866423072018694128099
    Line 359, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16537882276 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16537882276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 13.csrng_stress_all.45571955026705038344333242355323096715803432309358178927544099244533514308978
    Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/13.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 135363693820 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 135363693820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.csrng_stress_all.38577631808341380576961365443870122188131032553681758608999358065327802852140
    Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 321300309 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 321300309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 25.csrng_stress_all.35876750860196666951707667155750594426657719261492063896213840684564593575825
    Line 334, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 10835637345 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 10835637345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.csrng_stress_all.6216416424939964765350350738291437826124945744578237248937400593669029465978
    Line 334, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/39.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1585709295 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1585709295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

30.csrng_intr.67789532807212657244190221559882843345200536455645644088376620596718730169417
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 27434456 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 27434456 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  27434456 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  27434456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

98.csrng_intr.94674722754492371927220226079233440264292418918501198579231226830262094347123
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/98.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 48136877 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 48136877 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 48136877 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 48136877 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  48136877 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_push_pull_agent_*/push_pull_if.sv,158): Assertion AckAssertedOnlyWhenReqAsserted_A has failed has 1 failures:
- Test csrng_cmds has 1 failures.
  - 27.csrng_cmds.55021187060660348841992741449823548532377608504705410362663049607410152949334
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_cmds/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_push_pull_agent_0.1/push_pull_if.sv,158): (time 252690660 PS) Assertion tb.entropy_src_if.AckAssertedOnlyWhenReqAsserted_A has failed
  UVM_ERROR @ 252690660 ps: (push_pull_if.sv:158) [ASSERT FAILED] AckAssertedOnlyWhenReqAsserted_A
  UVM_INFO @ 252690660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 86.csrng_err.86962098915336426718787968364367051325455907055311377130467456595399400450774
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/86.csrng_err/latest/run.log
```
  UVM_ERROR @   3483192 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   3483192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```