CSRNG Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 9.000s 234.797us 50 50 100.00
V1 csr_hw_reset csrng_csr_hw_reset 8.000s 15.832us 5 5 100.00
V1 csr_rw csrng_csr_rw 5.000s 21.827us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 47.000s 2.264ms 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 12.000s 637.411us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 6.000s 127.020us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 5.000s 21.827us 20 20 100.00
csrng_csr_aliasing 12.000s 637.411us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 interrupts csrng_intr 10.000s 36.875us 197 200 98.50
V2 alerts csrng_alert 50.000s 3.900ms 500 500 100.00
V2 err csrng_err 17.000s 20.812us 494 500 98.80
V2 cmds csrng_cmds 6.500m 18.201ms 49 50 98.00
V2 life cycle csrng_cmds 6.500m 18.201ms 49 50 98.00
V2 stress_all csrng_stress_all 32.133m 145.749ms 44 50 88.00
V2 intr_test csrng_intr_test 14.000s 40.121us 50 50 100.00
V2 alert_test csrng_alert_test 26.000s 61.322us 50 50 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 18.000s 829.533us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 18.000s 829.533us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 8.000s 15.832us 5 5 100.00
csrng_csr_rw 5.000s 21.827us 20 20 100.00
csrng_csr_aliasing 12.000s 637.411us 5 5 100.00
csrng_same_csr_outstanding 8.000s 328.378us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 8.000s 15.832us 5 5 100.00
csrng_csr_rw 5.000s 21.827us 20 20 100.00
csrng_csr_aliasing 12.000s 637.411us 5 5 100.00
csrng_same_csr_outstanding 8.000s 328.378us 20 20 100.00
V2 TOTAL 1424 1440 98.89
V2S tl_intg_err csrng_sec_cm 8.000s 203.880us 5 5 100.00
csrng_tl_intg_err 23.000s 677.891us 20 20 100.00
V2S sec_cm_config_regwen csrng_regwen 10.000s 47.802us 50 50 100.00
csrng_csr_rw 5.000s 21.827us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 50.000s 3.900ms 500 500 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 32.133m 145.749ms 44 50 88.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_ctrl_mubi csrng_alert 50.000s 3.900ms 500 500 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
V2S sec_cm_constants_lc_gated csrng_stress_all 32.133m 145.749ms 44 50 88.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 50.000s 3.900ms 500 500 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 23.000s 677.891us 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
csrng_sec_cm 8.000s 203.880us 5 5 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 10.000s 36.875us 197 200 98.50
csrng_err 17.000s 20.812us 494 500 98.80
V2S TOTAL 75 75 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 28.217m 90.443ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1604 1630 98.40

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 9 9 5 55.56
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.15 98.23 95.85 98.86 96.54 91.90 100.00 97.32 90.42

Failure Buckets

Past Results