CSRNG Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	42.105us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	57.908us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	294.713us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	22.000s	350.254us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	158.967us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	189.598us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	294.713us	20	20	100.00
		csrng_csr_aliasing	6.000s	158.967us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	20.000s	90.764us	198	200	99.00
V2	alerts	csrng_alert	57.000s	3.599ms	500	500	100.00
V2	err	csrng_err	15.000s	24.448us	496	500	99.20
V2	cmds	csrng_cmds	10.717m	46.562ms	50	50	100.00
V2	life cycle	csrng_cmds	10.717m	46.562ms	50	50	100.00
V2	stress_all	csrng_stress_all	20.633m	49.160ms	48	50	96.00
V2	intr_test	csrng_intr_test	4.000s	35.116us	50	50	100.00
V2	alert_test	csrng_alert_test	10.000s	43.008us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	10.000s	202.270us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	10.000s	202.270us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	57.908us	5	5	100.00
		csrng_csr_rw	6.000s	294.713us	20	20	100.00
		csrng_csr_aliasing	6.000s	158.967us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	463.595us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	57.908us	5	5	100.00
		csrng_csr_rw	6.000s	294.713us	20	20	100.00
		csrng_csr_aliasing	6.000s	158.967us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	463.595us	20	20	100.00
V2		TOTAL			1432	1440	99.44
V2S	tl_intg_err	csrng_sec_cm	7.000s	105.748us	5	5	100.00
		csrng_tl_intg_err	25.000s	2.133ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	24.549us	50	50	100.00
		csrng_csr_rw	6.000s	294.713us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	57.000s	3.599ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	20.633m	49.160ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	57.000s	3.599ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	20.633m	49.160ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	57.000s	3.599ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	25.000s	2.133ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
		csrng_sec_cm	7.000s	105.748us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	20.000s	90.764us	198	200	99.00
		csrng_err	15.000s	24.448us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	23.733m	71.596ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1612	1630	98.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.11	98.21	95.79	98.81	96.54	91.84	100.00	97.32	90.32

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.50576702236122911855680343653559074490978843793277130579642070013907445738674
    Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15761144725 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15761144725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.88847477799970342752981746794018994634042985489242095375642424567089354447320
    Line 293, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15517601893 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 15517601893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 3.csrng_stress_all_with_rand_reset.5453128480378779392783103414024706536497557589525851536895379596802426115655
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1231075150 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1231075150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.36407999760091377075587926262044996711657379310565844959268797587481588680447
    Line 355, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19806314396 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19806314396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

21.csrng_err.77351247141408598480351604765866239912604743358249256433827515468859472653975
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/21.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  21.csrng_err.3394285207
  
  coverage files:
    model(design data) :  /workspace/coverage/default/21.csrng_err.3394285207/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/21.csrng_err.3394285207/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 23, 2024 at 18:00:54 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

68.csrng_err.75564797543907407267605921141905763350615189432725443585222448309414130328043
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/68.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  68.csrng_err.4195066347
  
  coverage files:
    model(design data) :  /workspace/coverage/default/68.csrng_err.4195066347/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/68.csrng_err.4195066347/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 23, 2024 at 18:01:35 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

24.csrng_intr.21201668842535497931218289655190816701984753583129862801857567902965095671120
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 20908649 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 20908649 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  20908649 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  20908649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

104.csrng_intr.107890777188219585020120040246542560398658219129339787612692575330056908530370
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/104.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 10746816 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 10746816 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  10746816 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  10746816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 23.csrng_stress_all.25386791760631126778083469766310638153119295438503562872074621558773109956318
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/23.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  20556567 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  20556567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 46.csrng_stress_all.17366745071337333682454615623355574386010933780406941988085710394862610031424
    Line 342, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3115356100 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3115356100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```