CSRNG Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	114.098us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	41.075us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	54.275us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	43.000s	2.059ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	317.085us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	357.962us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	54.275us	20	20	100.00
		csrng_csr_aliasing	7.000s	317.085us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	129.866us	196	200	98.00
V2	alerts	csrng_alert	1.083m	4.949ms	500	500	100.00
V2	err	csrng_err	15.000s	108.262us	496	500	99.20
V2	cmds	csrng_cmds	9.683m	43.614ms	50	50	100.00
V2	life cycle	csrng_cmds	9.683m	43.614ms	50	50	100.00
V2	stress_all	csrng_stress_all	33.133m	128.227ms	50	50	100.00
V2	intr_test	csrng_intr_test	4.000s	10.516us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	16.444us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	29.000s	1.981ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	29.000s	1.981ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	41.075us	5	5	100.00
		csrng_csr_rw	4.000s	54.275us	20	20	100.00
		csrng_csr_aliasing	7.000s	317.085us	5	5	100.00
		csrng_same_csr_outstanding	12.000s	749.342us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	41.075us	5	5	100.00
		csrng_csr_rw	4.000s	54.275us	20	20	100.00
		csrng_csr_aliasing	7.000s	317.085us	5	5	100.00
		csrng_same_csr_outstanding	12.000s	749.342us	20	20	100.00
V2		TOTAL			1432	1440	99.44
V2S	tl_intg_err	csrng_sec_cm	42.000s	796.599us	5	5	100.00
		csrng_tl_intg_err	13.000s	213.351us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	26.085us	50	50	100.00
		csrng_csr_rw	4.000s	54.275us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	4.949ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	33.133m	128.227ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	4.949ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	33.133m	128.227ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	4.949ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	13.000s	213.351us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
		csrng_sec_cm	42.000s	796.599us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	129.866us	196	200	98.00
		csrng_err	15.000s	108.262us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.533h	420.373ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1612	1630	98.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.07	98.19	95.74	98.79	96.54	91.77	100.00	96.78	90.21

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.24055535887262014186364078873090982886768187014614453669069410293852016858306
    Line 326, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27510466930 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 27510466930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.59644349908577520900657738666431397515051020320348764667446714175684952167969
    Line 502, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14277454938 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14277454938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

74.csrng_err.18046573195221020990719129558754758868482129483585927325853887160365323210776
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/74.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  74.csrng_err.708399128
  
  coverage files:
    model(design data) :  /workspace/coverage/default/74.csrng_err.708399128/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/74.csrng_err.708399128/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 24, 2024 at 16:45:46 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

89.csrng_err.45877591961841144056964550405640904039774069008267488741818406662182399666718
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/89.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  89.csrng_err.3492571678
  
  coverage files:
    model(design data) :  /workspace/coverage/default/89.csrng_err.3492571678/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/89.csrng_err.3492571678/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 24, 2024 at 16:45:59 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

24.csrng_intr.11183339385888577214592956512916299908259778576168162178000946976538889912708
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/24.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 27781185 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 27781185 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  27781185 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  27781185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

62.csrng_intr.5745068304454299970711332531466703626906236946569664502684214813442310515724
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/62.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 52776064 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 52776064 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  52776064 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  52776064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 7.csrng_stress_all_with_rand_reset.52903994186376901539209987324071666446412256178799297691931931233039010952858
    Line 407, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9401107533 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9401107533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1767): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

66.csrng_intr.76276423553968591573557579182318356345354850850288408918038957113163564591701
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/66.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 22927035 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 22927035 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 22927035 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 22927035 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 22927035 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed