CSRNG Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	271.759us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	144.500us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	35.997us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	40.000s	1.729ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	137.720us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	387.681us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	35.997us	20	20	100.00
		csrng_csr_aliasing	7.000s	137.720us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	298.566us	196	200	98.00
V2	alerts	csrng_alert	1.167m	4.469ms	500	500	100.00
V2	err	csrng_err	13.000s	20.515us	499	500	99.80
V2	cmds	csrng_cmds	9.600m	50.865ms	50	50	100.00
V2	life cycle	csrng_cmds	9.600m	50.865ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.600m	71.535ms	46	50	92.00
V2	intr_test	csrng_intr_test	8.000s	32.308us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	79.653us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	10.000s	162.769us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	10.000s	162.769us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	144.500us	5	5	100.00
		csrng_csr_rw	5.000s	35.997us	20	20	100.00
		csrng_csr_aliasing	7.000s	137.720us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	443.752us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	144.500us	5	5	100.00
		csrng_csr_rw	5.000s	35.997us	20	20	100.00
		csrng_csr_aliasing	7.000s	137.720us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	443.752us	20	20	100.00
V2		TOTAL			1431	1440	99.38
V2S	tl_intg_err	csrng_sec_cm	7.000s	308.904us	5	5	100.00
		csrng_tl_intg_err	18.000s	326.874us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	101.906us	50	50	100.00
		csrng_csr_rw	5.000s	35.997us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.167m	4.469ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.600m	71.535ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.167m	4.469ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.600m	71.535ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.167m	4.469ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	18.000s	326.874us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
		csrng_sec_cm	7.000s	308.904us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	298.566us	196	200	98.00
		csrng_err	13.000s	20.515us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	24.617m	83.727ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1611	1630	98.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	98.26	95.90	98.89	96.59	91.90	100.00	97.32	90.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 1.csrng_stress_all_with_rand_reset.24348602831767535741194136612305027751256568015986184360555569924417831682147
    Line 390, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 83726696676 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 83726696676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.108823453136364229814984867630795250472271442571474560778579459020741475634558
    Line 332, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73041727810 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 73041727810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 0.csrng_stress_all_with_rand_reset.65375125133036447608286435319413001415477886144373218402156027388689200104768
    Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4928594716 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4928594716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.58275410156053985804868358644754755564546238147414503822337534463067388861772
    Line 333, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9448149210 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9448149210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 9.csrng_stress_all.44768502704156182901843203166000039819162145346123882191498966656249936041270
    Line 358, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 7628586766 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 7628586766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.csrng_stress_all.12159243705814156930651075893104916395397061154988590179000616331132594532486
    Line 359, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/18.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4276054548 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4276054548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

52.csrng_intr.90982561458460948038008988491012351410863367194911789554553386386244727758362
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/52.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 43214301 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 43214301 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  43214301 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  43214301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

84.csrng_intr.50236689465755235187112745224662094267229218894357032636847695659739895478545
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/84.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 12423309 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 12423309 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  12423309 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  12423309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 46.csrng_stress_all.80561020011296587256878747092318791819280956513413578266588756470960373763827
    Line 368, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 9432358930 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 9432358930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1767): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

98.csrng_intr.91228767354484403163320085771842293570655145194179441278194374439462438352066
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/98.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 11263403 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 11263403 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 11263403 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 11263403 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 11263403 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test csrng_err has 1 failures.

377.csrng_err.64094794743907110495795784945504315199517271971700293336349307717617741506829
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/377.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  377.csrng_err.3404769549
  
  coverage files:
    model(design data) :  /workspace/coverage/default/377.csrng_err.3404769549/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/377.csrng_err.3404769549/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 25, 2024 at 16:58:46 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1