CSRNG Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	64.270us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	32.617us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	88.549us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	47.000s	3.789ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	274.801us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	11.000s	276.942us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	88.549us	20	20	100.00
		csrng_csr_aliasing	8.000s	274.801us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	10.000s	126.708us	195	200	97.50
V2	alerts	csrng_alert	56.000s	4.816ms	500	500	100.00
V2	err	csrng_err	19.000s	26.899us	496	500	99.20
V2	cmds	csrng_cmds	6.700m	18.143ms	50	50	100.00
V2	life cycle	csrng_cmds	6.700m	18.143ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.533m	85.544ms	46	50	92.00
V2	intr_test	csrng_intr_test	8.000s	25.971us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	61.918us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	346.463us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	346.463us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	32.617us	5	5	100.00
		csrng_csr_rw	5.000s	88.549us	20	20	100.00
		csrng_csr_aliasing	8.000s	274.801us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	612.749us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	32.617us	5	5	100.00
		csrng_csr_rw	5.000s	88.549us	20	20	100.00
		csrng_csr_aliasing	8.000s	274.801us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	612.749us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	10.000s	172.279us	5	5	100.00
		csrng_tl_intg_err	15.000s	521.139us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	21.638us	50	50	100.00
		csrng_csr_rw	5.000s	88.549us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	56.000s	4.816ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.533m	85.544ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	56.000s	4.816ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.533m	85.544ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	56.000s	4.816ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	521.139us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
		csrng_sec_cm	10.000s	172.279us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	10.000s	126.708us	195	200	97.50
		csrng_err	19.000s	26.899us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.616h	190.415ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1607	1630	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	98.21	95.79	98.81	96.54	91.90	96.00	97.32	90.74

Failure Buckets

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 0.csrng_stress_all_with_rand_reset.82015199559702185462532997479642241737697766846801191054367813975309623889806
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9764992945 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9764992945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.3332966653870983893725369879380719126357359407817360745855572715875965960961
    Line 293, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25265722716 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 25265722716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed

has 5 failures:

Test csrng_intr has 5 failures.

3.csrng_intr.88811698030480592362386362103090826873143730065369092288709287893267341557500
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 21771350 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 21771350 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  21771350 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  21771350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.csrng_intr.76604106140925204581998641012041870521051148466244183935652792026339945303394
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 63357760 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 63357760 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  63357760 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  63357760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test csrng_stress_all_with_rand_reset has 5 failures.
  - 4.csrng_stress_all_with_rand_reset.59461315335002296884981228263327943574935077383315415418309620539119543784501
    Line 313, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9287287724 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9287287724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.70477176314216030592203707193716205671963075938545457969780335274558516556295
    Line 340, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 57310054833 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 57310054833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:
- Test csrng_stress_all has 4 failures.
  - 1.csrng_stress_all.80248024612450817164087317043581025285565115702214306943469852219192663760080
    Line 355, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 12999169814 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 12999169814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.csrng_stress_all.93550999401506738242656047065969926405460863770478762822124026432493830199315
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  32312842 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  32312842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

5.csrng_err.7105796796375958826131980631014577601637252823818843368330493744235368538738
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  5.csrng_err.653386354
  
  coverage files:
    model(design data) :  /workspace/coverage/default/5.csrng_err.653386354/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/5.csrng_err.653386354/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 05, 2024 at 16:29:33 PDT  (total: 00:00:05)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

284.csrng_err.12275639024387775511790274079836348240152860218263548166125581253336889886453
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/284.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  284.csrng_err.560531189
  
  coverage files:
    model(design data) :  /workspace/coverage/default/284.csrng_err.560531189/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/284.csrng_err.560531189/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 05, 2024 at 16:32:03 PDT  (total: 00:00:19)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 2 more failures.