CSRNG Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	26.013us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	30.740us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	67.978us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	627.256us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	597.425us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	327.955us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	67.978us	20	20	100.00
		csrng_csr_aliasing	12.000s	597.425us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	95.055us	196	200	98.00
V2	alerts	csrng_alert	1.000m	4.560ms	500	500	100.00
V2	err	csrng_err	10.000s	20.031us	498	500	99.60
V2	cmds	csrng_cmds	8.383m	26.706ms	50	50	100.00
V2	life cycle	csrng_cmds	8.383m	26.706ms	50	50	100.00
V2	stress_all	csrng_stress_all	30.850m	70.951ms	48	50	96.00
V2	intr_test	csrng_intr_test	5.000s	138.302us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	52.183us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	15.000s	534.245us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	15.000s	534.245us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	30.740us	5	5	100.00
		csrng_csr_rw	4.000s	67.978us	20	20	100.00
		csrng_csr_aliasing	12.000s	597.425us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	163.294us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	30.740us	5	5	100.00
		csrng_csr_rw	4.000s	67.978us	20	20	100.00
		csrng_csr_aliasing	12.000s	597.425us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	163.294us	20	20	100.00
V2		TOTAL			1432	1440	99.44
V2S	tl_intg_err	csrng_sec_cm	6.000s	244.233us	5	5	100.00
		csrng_tl_intg_err	19.000s	363.260us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	181.991us	50	50	100.00
		csrng_csr_rw	4.000s	67.978us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.000m	4.560ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	30.850m	70.951ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.000m	4.560ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	30.850m	70.951ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.000m	4.560ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	19.000s	363.260us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
		csrng_sec_cm	6.000s	244.233us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	95.055us	196	200	98.00
		csrng_err	10.000s	20.031us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	13.033m	9.259ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1612	1630	98.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	98.26	95.90	98.89	96.59	91.84	100.00	97.32	90.21

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.99178845898365752687784675021539640393965029257205765156204180431012002086877
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 872465725 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 872465725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.69114347234366283215674158107548604001246430828486645787871472310990940036150
    Line 300, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1247506373 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1247506373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 4.csrng_stress_all_with_rand_reset.71376619843590731178569161120031846555726949765915438886821601040642176803369
    Line 301, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6059186382 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6059186382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all_with_rand_reset.37611277088236873500386334708468304390731930738598778037366074041636838904315
    Line 350, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8345088128 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8345088128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

38.csrng_intr.84681336524383356233758551414205446868128896217230983132243319950911589240636
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/38.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 58928688 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 58928688 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  58928688 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  58928688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

54.csrng_intr.40465687939380427720018968053527867251262154740239682178068361538186019099762
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/54.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 41739139 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 41739139 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  41739139 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  41739139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 6.csrng_stress_all.13487048408299681900372199364101919249693501053371820544388957082486596364418
    Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 137741858 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 137741858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.csrng_stress_all.103677746060504079555025778907527129473873128200881291290629938529838865364531
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/33.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  62514254 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  62514254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

61.csrng_err.43756910109182418559933949573228154636191391618776808307796101147611962801316
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/61.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  61.csrng_err.4122737828
  
  coverage files:
    model(design data) :  /workspace/coverage/default/61.csrng_err.4122737828/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/61.csrng_err.4122737828/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 01, 2024 at 16:29:37 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

241.csrng_err.11852230076087264004669813395046130528101509689783364040880493065267862969420
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/241.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  241.csrng_err.2731416652
  
  coverage files:
    model(design data) :  /workspace/coverage/default/241.csrng_err.2731416652/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/241.csrng_err.2731416652/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 01, 2024 at 16:31:07 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1