CSRNG Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	6.000s	325.357us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	25.923us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	301.746us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	45.000s	2.140ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	210.640us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	18.000s	21.008us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	301.746us	20	20	100.00
		csrng_csr_aliasing	6.000s	210.640us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	7.000s	403.643us	195	200	97.50
V2	alerts	csrng_alert	1.017m	4.591ms	500	500	100.00
V2	err	csrng_err	5.000s	35.415us	497	500	99.40
V2	cmds	csrng_cmds	14.933m	88.404ms	50	50	100.00
V2	life cycle	csrng_cmds	14.933m	88.404ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.617m	24.093ms	47	50	94.00
V2	intr_test	csrng_intr_test	7.000s	37.666us	50	50	100.00
V2	alert_test	csrng_alert_test	4.000s	53.712us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	251.532us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	251.532us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	25.923us	5	5	100.00
		csrng_csr_rw	7.000s	301.746us	20	20	100.00
		csrng_csr_aliasing	6.000s	210.640us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	212.221us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	25.923us	5	5	100.00
		csrng_csr_rw	7.000s	301.746us	20	20	100.00
		csrng_csr_aliasing	6.000s	210.640us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	212.221us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	9.000s	236.755us	5	5	100.00
		csrng_tl_intg_err	20.000s	1.311ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	98.948us	50	50	100.00
		csrng_csr_rw	7.000s	301.746us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.017m	4.591ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.617m	24.093ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.017m	4.591ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.617m	24.093ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.017m	4.591ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	20.000s	1.311ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
		csrng_sec_cm	9.000s	236.755us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	403.643us	195	200	97.50
		csrng_err	5.000s	35.415us	497	500	99.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.160h	164.331ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1609	1630	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	98.26	95.90	98.89	96.59	91.84	100.00	97.32	90.63

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.51880052421872307851329563464161422322642269232308645647143604902153503760320
    Line 512, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 76540040439 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 76540040439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.11869220590399105592775354200555010482295463330815922566242917132147543565152
    Line 331, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23616360696 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 23616360696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 5 failures:

Test csrng_intr has 5 failures.

94.csrng_intr.81566381129691680899089454355776380048492489174013653771832744845006158112826
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/94.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 30993060 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 30993060 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  30993060 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  30993060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

95.csrng_intr.38015715635810797922653396764378401908777665523620476694716468729256552513982
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/95.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 15676996 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 15676996 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  15676996 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  15676996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

345.csrng_err.19901258304758358846995173929090238523097971167642504978453501893305860784688
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/345.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  345.csrng_err.2922283568
  
  coverage files:
    model(design data) :  /workspace/coverage/default/345.csrng_err.2922283568/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/345.csrng_err.2922283568/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 02, 2024 at 17:50:05 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

447.csrng_err.39246133247866669125726059007494163534883413213841394372126662745904631545621
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/447.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  447.csrng_err.2745204501
  
  coverage files:
    model(design data) :  /workspace/coverage/default/447.csrng_err.2745204501/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/447.csrng_err.2745204501/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 02, 2024 at 17:50:41 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 3.csrng_stress_all.18091555231617309338101771558209242128456313436943149479783640367184053646429
    Line 372, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 12585880020 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 12585880020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.csrng_stress_all.19212843014558264448297331589861123598295647895155349139473553260116101331696
    Line 344, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 6607824140 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 6607824140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 5.csrng_stress_all_with_rand_reset.74021943621324888744220708072977306757688474064736351008863871296775761123491
    Line 304, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1335313741 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1335313741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.csrng_stress_all_with_rand_reset.40708164554507292217883936592121565883702480727868836292585216402117825676051
    Line 344, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 76879856767 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 76879856767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 8.csrng_stress_all.46699078121084890938263162711246305926390579867869865136786858486761607350165
    Line 348, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5390863528 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5390863528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```