CSRNG Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	46.262us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	36.006us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	137.800us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	1.456ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	362.289us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	247.401us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	137.800us	20	20	100.00
		csrng_csr_aliasing	9.000s	362.289us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	48.016us	198	200	99.00
V2	alerts	csrng_alert	1.133m	5.494ms	500	500	100.00
V2	err	csrng_err	14.000s	39.920us	496	500	99.20
V2	cmds	csrng_cmds	6.000m	17.840ms	50	50	100.00
V2	life cycle	csrng_cmds	6.000m	17.840ms	50	50	100.00
V2	stress_all	csrng_stress_all	23.433m	51.244ms	49	50	98.00
V2	intr_test	csrng_intr_test	9.000s	106.419us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	65.863us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	11.000s	248.150us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	11.000s	248.150us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	36.006us	5	5	100.00
		csrng_csr_rw	5.000s	137.800us	20	20	100.00
		csrng_csr_aliasing	9.000s	362.289us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	553.391us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	36.006us	5	5	100.00
		csrng_csr_rw	5.000s	137.800us	20	20	100.00
		csrng_csr_aliasing	9.000s	362.289us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	553.391us	20	20	100.00
V2		TOTAL			1433	1440	99.51
V2S	tl_intg_err	csrng_sec_cm	7.000s	281.883us	5	5	100.00
		csrng_tl_intg_err	15.000s	262.092us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	22.662us	50	50	100.00
		csrng_csr_rw	5.000s	137.800us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.133m	5.494ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	23.433m	51.244ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.133m	5.494ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	23.433m	51.244ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.133m	5.494ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	262.092us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
		csrng_sec_cm	7.000s	281.883us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	48.016us	198	200	99.00
		csrng_err	14.000s	39.920us	496	500	99.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	59.300m	180.955ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.06	98.19	95.74	98.79	96.54	91.77	100.00	96.78	90.11

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.57639966733756687893836020882390210880876424513970278086370207543653813959670
    Line 353, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10089974364 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10089974364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.12115667399630748253446534661739480349948116960304503399950652778355803564010
    Line 365, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53803807617 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 53803807617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 2.csrng_stress_all_with_rand_reset.15062852902777944122666049484139591192769626687285899350681489171731677388332
    Line 348, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5456428647 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5456428647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.csrng_stress_all_with_rand_reset.9534712011533448197601557921102711887185926835767707948344293029907033702882
    Line 299, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2796159915 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2796159915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 4 failures:

Test csrng_err has 4 failures.

131.csrng_err.19368416159853377640434407786722285676048476698497379442926537926018594953402
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/131.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  131.csrng_err.1153620154
  
  coverage files:
    model(design data) :  /workspace/coverage/default/131.csrng_err.1153620154/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/131.csrng_err.1153620154/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 30, 2024 at 18:05:13 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

211.csrng_err.82325864305257806850105924100442367205957156570957473894300004174871985639148
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/211.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  211.csrng_err.4271886060
  
  coverage files:
    model(design data) :  /workspace/coverage/default/211.csrng_err.4271886060/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/211.csrng_err.4271886060/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 30, 2024 at 18:06:16 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 2 failures:

Test csrng_intr has 2 failures.

77.csrng_intr.6180114384006055347514356689309989005726754461143637726691538469886130431150
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/77.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 11028633 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 11028633 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  11028633 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  11028633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

173.csrng_intr.87870582763356356425238335889388788706070052048805269765353174144874645457554
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/173.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 10923857 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 10923857 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  10923857 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  10923857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 10.csrng_stress_all.16178652310606720841941445296709143752083328207625343169953460597156392844407
    Line 316, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  54146699 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  54146699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```