CSRNG Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	115.392us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	17.276us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	105.073us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	59.000s	5.211ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	154.785us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	184.819us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	105.073us	20	20	100.00
		csrng_csr_aliasing	7.000s	154.785us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	45.093us	196	200	98.00
V2	alerts	csrng_alert	1.200m	5.853ms	500	500	100.00
V2	err	csrng_err	14.000s	41.895us	494	500	98.80
V2	cmds	csrng_cmds	16.017m	98.506ms	50	50	100.00
V2	life cycle	csrng_cmds	16.017m	98.506ms	50	50	100.00
V2	stress_all	csrng_stress_all	19.250m	70.481ms	49	50	98.00
V2	intr_test	csrng_intr_test	4.000s	16.665us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	18.884us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	22.000s	1.432ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	22.000s	1.432ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	17.276us	5	5	100.00
		csrng_csr_rw	5.000s	105.073us	20	20	100.00
		csrng_csr_aliasing	7.000s	154.785us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	102.624us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	17.276us	5	5	100.00
		csrng_csr_rw	5.000s	105.073us	20	20	100.00
		csrng_csr_aliasing	7.000s	154.785us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	102.624us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	10.000s	74.236us	5	5	100.00
		csrng_tl_intg_err	15.000s	827.059us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	38.770us	50	50	100.00
		csrng_csr_rw	5.000s	105.073us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.200m	5.853ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	19.250m	70.481ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.200m	5.853ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	19.250m	70.481ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.200m	5.853ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	827.059us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
		csrng_sec_cm	10.000s	74.236us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	45.093us	196	200	98.00
		csrng_err	14.000s	41.895us	494	500	98.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.039h	150.077ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1609	1630	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	98.26	95.90	98.89	96.59	91.90	100.00	97.32	90.42

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.22432459429211787314025865532760171768061172789813525437500072280635053414710
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1515158887 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1515158887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.97202481052295362692450828638870506344366737997641692056530041486291612353561
    Line 305, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7760674045 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7760674045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:

Test csrng_err has 5 failures.

26.csrng_err.22989014403679702808673876443588231762962860439776072897189517344571513140110
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  26.csrng_err.2130211726
  
  coverage files:
    model(design data) :  /workspace/coverage/default/26.csrng_err.2130211726/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/26.csrng_err.2130211726/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 31, 2024 at 16:46:06 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

86.csrng_err.1274282124702613988212998461913595938968889246658750435638404418005186562995
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/86.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  86.csrng_err.1728236467
  
  coverage files:
    model(design data) :  /workspace/coverage/default/86.csrng_err.1728236467/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/86.csrng_err.1728236467/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Jul 31, 2024 at 16:46:35 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 3 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

17.csrng_intr.60045032473663296618788402137248146120503931521666045341973811590753558358280
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 14813237 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 14813237 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  14813237 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  14813237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

168.csrng_intr.63561543537660477540971581725552921967079121285748510839033669975021988591158
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/168.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 14289791 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 14289791 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  14289791 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  14289791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 4.csrng_stress_all_with_rand_reset.19416954683200085268479520909526557096571363303220949901868922074530704222023
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 967022536 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 967022536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all_with_rand_reset.97955012629230896916391406569788003540368160369324763169781498342316155817600
    Line 505, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 150077396456 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 150077396456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 46.csrng_stress_all.36047583229604503965033984383300672098328820509504091325006831953062122634092
    Line 337, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/46.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 10786711995 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 10786711995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1767): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

87.csrng_intr.41238764039676230145757242795043209719700700541565982782069259494947084542457
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/87.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 72330295 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 72330295 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 72330295 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 72330295 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 72330295 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed

UVM_ERROR (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 433.csrng_err.19087072973409393392745692269154007420475613181576511068997675847081847383308
    Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/433.csrng_err/latest/run.log
```
  UVM_ERROR @   6212686 ps: (csr_utils_pkg.sv:478) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   6212686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```