CSRNG Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	337.017us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	142.438us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	21.648us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	19.000s	526.810us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	629.824us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	299.256us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	21.648us	20	20	100.00
		csrng_csr_aliasing	10.000s	629.824us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	6.000s	192.518us	195	200	97.50
V2	alerts	csrng_alert	1.067m	5.508ms	500	500	100.00
V2	err	csrng_err	9.000s	22.981us	497	500	99.40
V2	cmds	csrng_cmds	6.133m	22.803ms	50	50	100.00
V2	life cycle	csrng_cmds	6.133m	22.803ms	50	50	100.00
V2	stress_all	csrng_stress_all	30.517m	154.287ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	100.431us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	249.913us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	470.237us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	470.237us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	142.438us	5	5	100.00
		csrng_csr_rw	4.000s	21.648us	20	20	100.00
		csrng_csr_aliasing	10.000s	629.824us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	98.235us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	142.438us	5	5	100.00
		csrng_csr_rw	4.000s	21.648us	20	20	100.00
		csrng_csr_aliasing	10.000s	629.824us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	98.235us	20	20	100.00
V2		TOTAL			1429	1440	99.24
V2S	tl_intg_err	csrng_sec_cm	7.000s	89.690us	5	5	100.00
		csrng_tl_intg_err	31.000s	1.605ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	98.647us	50	50	100.00
		csrng_csr_rw	4.000s	21.648us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.067m	5.508ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	30.517m	154.287ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.067m	5.508ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	30.517m	154.287ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.067m	5.508ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	31.000s	1.605ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
		csrng_sec_cm	7.000s	89.690us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	192.518us	195	200	97.50
		csrng_err	9.000s	22.981us	497	500	99.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.233h	61.786ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1609	1630	98.71

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	98.26	95.90	98.89	96.59	91.84	100.00	97.32	90.42

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.41718829795350727878887456436498913989641368908844932574758677413972006124114
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10943585703 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10943585703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.73565685231416097520658978125435986020117791321311093642015100060147440016858
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3389896113 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3389896113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 1.csrng_stress_all_with_rand_reset.76729073274662118790920546342640079290467365593626772086945516992119283323092
    Line 382, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10231168081 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10231168081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.113983833519342979057216874969912846829391744738232462942051110247693110936336
    Line 821, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 61785766614 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 61785766614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 4 failures:

Test csrng_intr has 4 failures.

15.csrng_intr.40697315024330687059015850661832557734641313052192454001103332635583862515123
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 16337419 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 16337419 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  16337419 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  16337419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

113.csrng_intr.9615211023955435534605160591255180130826602979545925229449094999289693399784
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/113.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 13854717 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 13854717 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @  13854717 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @  13854717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 3 failures:

Test csrng_err has 3 failures.

7.csrng_err.65084936787245586789522078183651914190322795449794584164528796248733840596521
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  7.csrng_err.707550761
  
  coverage files:
    model(design data) :  /workspace/coverage/default/7.csrng_err.707550761/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/7.csrng_err.707550761/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 06, 2024 at 16:47:50 PDT  (total: 00:00:04)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

109.csrng_err.51144384009491297785101936970763361603902527280598035235246667189698660557845
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/109.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  109.csrng_err.611214357
  
  coverage files:
    model(design data) :  /workspace/coverage/default/109.csrng_err.611214357/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/109.csrng_err.611214357/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 06, 2024 at 16:49:31 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 30.csrng_stress_all.38073987645242151139899757718872539908282990018737135601409339269202044537622
    Line 343, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 14337246043 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 14337246043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.csrng_stress_all.100788799890177502834218285771443494169021107370348882818409687437689211495396
    Line 330, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/43.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 456887075 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 456887075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 36.csrng_stress_all.43340566135879879994228090331761406352274112768972524075634200467365640725867
    Line 324, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 4985952927 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 4985952927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1767): Assertion CsrngUniZeroizeFips_A has failed has 1 failures:

Test csrng_intr has 1 failures.

111.csrng_intr.115521004987935258258171670743196915115048272201468056737140027325919957526389
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/111.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1767): (time 30377829 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeFips_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 30377829 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 30377829 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 30377829 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 30377829 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed