CSRNG Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	19.674us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	17.880us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	59.530us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	41.000s	2.915ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	13.000s	890.908us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	65.188us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	59.530us	20	20	100.00
		csrng_csr_aliasing	13.000s	890.908us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	16.000s	283.499us	197	200	98.50
V2	alerts	csrng_alert	1.033m	4.547ms	500	500	100.00
V2	err	csrng_err	23.000s	36.963us	498	500	99.60
V2	cmds	csrng_cmds	11.033m	55.325ms	50	50	100.00
V2	life cycle	csrng_cmds	11.033m	55.325ms	50	50	100.00
V2	stress_all	csrng_stress_all	32.467m	60.579ms	46	50	92.00
V2	intr_test	csrng_intr_test	5.000s	47.736us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	19.637us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	158.978us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	158.978us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	17.880us	5	5	100.00
		csrng_csr_rw	8.000s	59.530us	20	20	100.00
		csrng_csr_aliasing	13.000s	890.908us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	52.343us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	17.880us	5	5	100.00
		csrng_csr_rw	8.000s	59.530us	20	20	100.00
		csrng_csr_aliasing	13.000s	890.908us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	52.343us	20	20	100.00
V2		TOTAL			1431	1440	99.38
V2S	tl_intg_err	csrng_sec_cm	14.000s	76.348us	5	5	100.00
		csrng_tl_intg_err	11.000s	483.165us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	158.540us	50	50	100.00
		csrng_csr_rw	8.000s	59.530us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.033m	4.547ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.467m	60.579ms	46	50	92.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.033m	4.547ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.467m	60.579ms	46	50	92.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.033m	4.547ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	483.165us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
		csrng_sec_cm	14.000s	76.348us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	16.000s	283.499us	197	200	98.50
		csrng_err	23.000s	36.963us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.209h	46.162ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1611	1630	98.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	98.26	95.90	98.89	96.59	91.84	100.00	97.32	90.42

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.60703077675147577465606829720009071518124655705973522522438731095461903181750
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33700104684 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 33700104684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.94028365935287040839991042450980638662659508850634253700785562845615770513501
    Line 298, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1076359815 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1076359815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 1.csrng_stress_all_with_rand_reset.38221703177419557545894876500507722811456889950184784075823557940458645650567
    Line 290, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1065865234 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1065865234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.40182947009662448137039690356419028338746582741684778668362091572621090683046
    Line 357, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 89162803884 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 89162803884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_core.sv,1768): Assertion CsrngUniZeroizeKey_A has failed has 3 failures:

Test csrng_intr has 3 failures.

69.csrng_intr.85066844314823238434819922867287533806333572580504267682525523812222105795917
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/69.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 172985600 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 172985600 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  UVM_ERROR @ 172985600 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A
  UVM_INFO @ 172985600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

113.csrng_intr.20129204258177992073941876977317051101365902381216958920767990101531500646311
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/113.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1768): (time 11137135 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeKey_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1769): (time 11137135 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeV_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1770): (time 11137135 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeRc_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_core.sv,1771): (time 11137135 PS) Assertion tb.dut.u_csrng_core.CsrngUniZeroizeSts_A has failed
  UVM_ERROR @  11137135 ps: (csrng_core.sv:1768) [ASSERT FAILED] CsrngUniZeroizeKey_A

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 1.csrng_stress_all.63837864772829232967770447470014695153616250151317690451577621712259815973259
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  11617594 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  11617594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.csrng_stress_all.19803784393679092431133849873751050945961509138220239050528583003084545943272
    Line 363, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 2717321224 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2717321224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 4.csrng_stress_all.5233960039994573486486391234588721931276868400949418025339810478130636601345
    Line 344, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 23346939424 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 23346939424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.csrng_stress_all.115579400784470503014731176276907395133942844667581997369407430652434440891560
    Line 319, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  20133503 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  20133503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test csrng_err has 2 failures.

121.csrng_err.93980169525999254378293485304635283506824549357378871698860702587746673295459
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/121.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  121.csrng_err.858849379
  
  coverage files:
    model(design data) :  /workspace/coverage/default/121.csrng_err.858849379/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/121.csrng_err.858849379/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 07, 2024 at 16:50:51 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1

293.csrng_err.90488360685772207854185444835808774800495147338829253777462997102231871720390
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/293.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  293.csrng_err.512658374
  
  coverage files:
    model(design data) :  /workspace/coverage/default/293.csrng_err.512658374/icc_57048ec4_40c9e8d2.ucm
    data               :  /workspace/coverage/default/293.csrng_err.512658374/icc_57048ec4_40c9e8d2.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Aug 07, 2024 at 16:51:30 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 1