CSRNG Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	27.068us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	23.361us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	21.837us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	26.000s	541.693us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	5.000s	71.487us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	11.000s	400.217us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	21.837us	20	20	100.00
		csrng_csr_aliasing	5.000s	71.487us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	22.000s	1.301ms	198	200	99.00
V2	alerts	csrng_alert	50.000s	3.531ms	500	500	100.00
V2	err	csrng_err	15.000s	27.068us	500	500	100.00
V2	cmds	csrng_cmds	6.950m	32.377ms	50	50	100.00
V2	life cycle	csrng_cmds	6.950m	32.377ms	50	50	100.00
V2	stress_all	csrng_stress_all	34.683m	84.485ms	47	50	94.00
V2	intr_test	csrng_intr_test	8.000s	13.893us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	17.928us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	1.071ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	1.071ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	23.361us	5	5	100.00
		csrng_csr_rw	4.000s	21.837us	20	20	100.00
		csrng_csr_aliasing	5.000s	71.487us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	42.317us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	23.361us	5	5	100.00
		csrng_csr_rw	4.000s	21.837us	20	20	100.00
		csrng_csr_aliasing	5.000s	71.487us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	42.317us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_sec_cm	9.000s	784.192us	5	5	100.00
		csrng_tl_intg_err	11.000s	268.925us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	14.000s	95.545us	50	50	100.00
		csrng_csr_rw	4.000s	21.837us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	50.000s	3.531ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	34.683m	84.485ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	50.000s	3.531ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	34.683m	84.485ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	50.000s	3.531ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	268.925us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
		csrng_sec_cm	9.000s	784.192us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	22.000s	1.301ms	198	200	99.00
		csrng_err	15.000s	27.068us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	13.183m	23.845ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1615	1630	99.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	98.30	96.00	98.99	96.65	91.77	100.00	96.78	90.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.66371983947357636345137305832635162273621248273318123874107532046068130188717
    Line 306, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11377302977 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11377302977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.27559951593894856373258608971772922157913038966108521713444945086287647693404
    Line 355, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19910540264 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 19910540264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test csrng_stress_all_with_rand_reset has 2 failures.
  - 1.csrng_stress_all_with_rand_reset.107499773048572195682656334089093147825086955669899347325676274813009634440905
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 683732597 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 683732597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.csrng_stress_all_with_rand_reset.45214350756874642699017823796970943006297539768550166055377654647208308243058
    Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26038956677 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26038956677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 2.csrng_stress_all.80244033599753138577668679739714751171389846330975531963326512316912960093004
    Line 336, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 10879929155 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 10879929155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.csrng_stress_all.102544614138445031395961739317951282911158543435734657854379945700645546771371
    Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 199934975 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 199934975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

37.csrng_intr.6408996272992777983566562205764779772861040156930162087161999902161202362430
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/37.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 849197157 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 849197157 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 849197157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

177.csrng_intr.89264390477884990139472144051748764188487797387128535997246663100890474047558
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/177.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 127405398 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 127405398 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 127405398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 11.csrng_stress_all.42563116681822909736624613946979283211720160163224179003856632462707027638929
    Line 322, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  78279382 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  78279382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```