CSRNG Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	14.000s	60.788us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	34.093us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	300.565us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.000s	746.711us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	214.433us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	128.380us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	300.565us	20	20	100.00
		csrng_csr_aliasing	6.000s	214.433us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	25.000s	1.918ms	199	200	99.50
V2	alerts	csrng_alert	1.317m	6.770ms	500	500	100.00
V2	err	csrng_err	14.000s	21.938us	500	500	100.00
V2	cmds	csrng_cmds	7.633m	39.514ms	50	50	100.00
V2	life cycle	csrng_cmds	7.633m	39.514ms	50	50	100.00
V2	stress_all	csrng_stress_all	13.983m	42.840ms	49	50	98.00
V2	intr_test	csrng_intr_test	4.000s	38.006us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	22.191us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	726.543us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	726.543us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	34.093us	5	5	100.00
		csrng_csr_rw	6.000s	300.565us	20	20	100.00
		csrng_csr_aliasing	6.000s	214.433us	5	5	100.00
		csrng_same_csr_outstanding	12.000s	814.533us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	34.093us	5	5	100.00
		csrng_csr_rw	6.000s	300.565us	20	20	100.00
		csrng_csr_aliasing	6.000s	214.433us	5	5	100.00
		csrng_same_csr_outstanding	12.000s	814.533us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	8.000s	127.643us	5	5	100.00
		csrng_tl_intg_err	12.000s	182.996us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	22.220us	50	50	100.00
		csrng_csr_rw	6.000s	300.565us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.317m	6.770ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	13.983m	42.840ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.317m	6.770ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	13.983m	42.840ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.317m	6.770ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	182.996us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
		csrng_sec_cm	8.000s	127.643us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	25.000s	1.918ms	199	200	99.50
		csrng_err	14.000s	21.938us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	24.900m	85.025ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1618	1630	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.34	98.37	96.16	99.09	96.81	91.77	100.00	97.14	90.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.42399886516748195844736377299613790146353702590314228821839816956562732042336
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 996507978 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 996507978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.58153746353513762120986359160758666057709067647778622689462728779096760096324
    Line 316, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16683444397 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16683444397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 1.csrng_stress_all_with_rand_reset.85551710310330365753916482205412553965195233008555053812700014078685351572139
    Line 415, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10572784097 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10572784097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.33413455796694134073329066494437788872378402744305789417719062214484588451087
    Line 415, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9717821142 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9717821142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 14.csrng_stress_all.81244399400633780619601898264182369464620585708539906558591157874017266754243
    Line 337, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 194893084 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 194893084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

35.csrng_intr.46383574363390872816081833171624562314607042656552972112397548986371251720766
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 105268746 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 105268746 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 105268746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---