CSRNG Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	137.089us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	9.000s	20.736us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	23.330us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	32.000s	351.309us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	644.343us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	118.239us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	23.330us	20	20	100.00
		csrng_csr_aliasing	11.000s	644.343us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	20.000s	152.145us	200	200	100.00
V2	alerts	csrng_alert	1.567m	8.067ms	500	500	100.00
V2	err	csrng_err	18.000s	20.968us	500	500	100.00
V2	cmds	csrng_cmds	8.400m	41.686ms	50	50	100.00
V2	life cycle	csrng_cmds	8.400m	41.686ms	50	50	100.00
V2	stress_all	csrng_stress_all	22.000m	80.719ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	13.358us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	28.747us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	518.798us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	518.798us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	9.000s	20.736us	5	5	100.00
		csrng_csr_rw	8.000s	23.330us	20	20	100.00
		csrng_csr_aliasing	11.000s	644.343us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	144.319us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	9.000s	20.736us	5	5	100.00
		csrng_csr_rw	8.000s	23.330us	20	20	100.00
		csrng_csr_aliasing	11.000s	644.343us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	144.319us	20	20	100.00
V2		TOTAL			1439	1440	99.93
V2S	tl_intg_err	csrng_sec_cm	11.000s	86.723us	5	5	100.00
		csrng_tl_intg_err	11.000s	471.210us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	14.269us	50	50	100.00
		csrng_csr_rw	8.000s	23.330us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.567m	8.067ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	22.000m	80.719ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.567m	8.067ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	22.000m	80.719ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.567m	8.067ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	471.210us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
		csrng_sec_cm	11.000s	86.723us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	20.000s	152.145us	200	200	100.00
		csrng_err	18.000s	20.968us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.617m	1.548ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1619	1630	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.33	98.37	96.16	99.07	96.76	91.84	100.00	97.32	90.65

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test csrng_stress_all_with_rand_reset has 7 failures.

    • 0.csrng_stress_all_with_rand_reset.6744439079857387543660988956808406962795776441284415457935748148717448752894
      Line 293, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1943473639 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1943473639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.csrng_stress_all_with_rand_reset.55029864999444393568959702304327633679040170803083060420371275544182588964567
      Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 111703659 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 111703659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test csrng_stress_all_with_rand_reset has 2 failures.

    • 6.csrng_stress_all_with_rand_reset.86913067681816499077599088819215818934465736643100885231297203662756561493188
      Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 106305993 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 106305993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.csrng_stress_all_with_rand_reset.82962291415988515537374166944231533385899098175538238034904263275123062234608
      Line 294, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3222852146 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3222852146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:

  • Test csrng_stress_all has 1 failures.

    • 1.csrng_stress_all.13069868085480496011793613569774524985996533092454123118538699456514609625235
      Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log

        UVM_ERROR @ 101158990 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 101158990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:

  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 8.csrng_stress_all_with_rand_reset.57241975357481629829319081689718871862098685420907562698982303055286371925678
      Line 293, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  21603623 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
        UVM_INFO @  21603623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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