CSRNG Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	16.839us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	13.000s	42.478us	5	5	100.00
V1	csr_rw	csrng_csr_rw	10.000s	194.026us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.283m	5.893ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	261.341us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	77.224us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	10.000s	194.026us	20	20	100.00
		csrng_csr_aliasing	8.000s	261.341us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	21.000s	1.244ms	200	200	100.00
V2	alerts	csrng_alert	1.167m	5.255ms	500	500	100.00
V2	err	csrng_err	14.000s	114.774us	498	500	99.60
V2	cmds	csrng_cmds	4.583m	6.745ms	50	50	100.00
V2	life cycle	csrng_cmds	4.583m	6.745ms	50	50	100.00
V2	stress_all	csrng_stress_all	30.250m	156.939ms	48	50	96.00
V2	intr_test	csrng_intr_test	19.000s	94.067us	50	50	100.00
V2	alert_test	csrng_alert_test	13.000s	21.830us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	30.000s	2.343ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	30.000s	2.343ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	13.000s	42.478us	5	5	100.00
		csrng_csr_rw	10.000s	194.026us	20	20	100.00
		csrng_csr_aliasing	8.000s	261.341us	5	5	100.00
		csrng_same_csr_outstanding	13.000s	17.182us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	13.000s	42.478us	5	5	100.00
		csrng_csr_rw	10.000s	194.026us	20	20	100.00
		csrng_csr_aliasing	8.000s	261.341us	5	5	100.00
		csrng_same_csr_outstanding	13.000s	17.182us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	10.000s	489.589us	5	5	100.00
		csrng_tl_intg_err	14.000s	458.080us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	19.529us	50	50	100.00
		csrng_csr_rw	10.000s	194.026us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.167m	5.255ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	30.250m	156.939ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.167m	5.255ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	30.250m	156.939ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.167m	5.255ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	458.080us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
		csrng_sec_cm	10.000s	489.589us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	21.000s	1.244ms	200	200	100.00
		csrng_err	14.000s	114.774us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.000m	6.074ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.22	98.30	96.00	98.96	96.70	91.84	100.00	96.78	90.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:849) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 0.csrng_stress_all_with_rand_reset.64930197862871572931698786281583314749295249722219194069621799862061463177223
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6073719902 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6073719902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.45316463475696855525269255841489660179516485665813353087800385875220639134328
    Line 284, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 939348749 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 939348749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:849) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 2.csrng_stress_all_with_rand_reset.26112459462531034033979302686303682943994917503971419881662655210461849637770
    Line 289, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 533021611 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 533021611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.115533704760707874485374078366544253712934892575160358464692740722965458683590
    Line 285, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 413677819 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 413677819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 2 failures:

Test csrng_err has 2 failures.

123.csrng_err.65967908955205636330727254736527200284631927552266778580251600557263625594512
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/123.csrng_err/latest/run.log

  UVM_ERROR @  11426211 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  11426211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

293.csrng_err.97108931852282250362804817530259087987973898182392404962645162977672269040722
Line 314, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/293.csrng_err/latest/run.log

  UVM_ERROR @   4887982 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   4887982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 3.csrng_stress_all_with_rand_reset.726519962614009016899151232765805557821136133879890831584226070980005878566
    Line 290, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  17422377 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  17422377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 9.csrng_stress_all.24343872838584241462631349845751676595647692481387276912153963691243162590705
    Line 334, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 6326638873 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 6326638873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 15.csrng_stress_all.73311172099538293802844465510349354817007788791962373638661122536716166542346
    Line 318, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  40536210 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  40536210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```