CSRNG Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	22.481us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	72.710us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	36.940us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	26.000s	709.497us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	561.241us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	118.347us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	36.940us	20	20	100.00
		csrng_csr_aliasing	11.000s	561.241us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	26.000s	1.138ms	200	200	100.00
V2	alerts	csrng_alert	1.150m	5.513ms	500	500	100.00
V2	err	csrng_err	15.000s	49.165us	500	500	100.00
V2	cmds	csrng_cmds	7.150m	41.675ms	50	50	100.00
V2	life cycle	csrng_cmds	7.150m	41.675ms	50	50	100.00
V2	stress_all	csrng_stress_all	24.900m	58.556ms	43	50	86.00
V2	intr_test	csrng_intr_test	13.000s	24.630us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	16.809us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	321.715us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	321.715us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	72.710us	5	5	100.00
		csrng_csr_rw	4.000s	36.940us	20	20	100.00
		csrng_csr_aliasing	11.000s	561.241us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	28.986us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	72.710us	5	5	100.00
		csrng_csr_rw	4.000s	36.940us	20	20	100.00
		csrng_csr_aliasing	11.000s	561.241us	5	5	100.00
		csrng_same_csr_outstanding	14.000s	28.986us	20	20	100.00
V2		TOTAL			1433	1440	99.51
V2S	tl_intg_err	csrng_sec_cm	15.000s	132.578us	5	5	100.00
		csrng_tl_intg_err	18.000s	1.563ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	13.479us	50	50	100.00
		csrng_csr_rw	4.000s	36.940us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.150m	5.513ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	24.900m	58.556ms	43	50	86.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.150m	5.513ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	24.900m	58.556ms	43	50	86.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.150m	5.513ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	18.000s	1.563ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
		csrng_sec_cm	15.000s	132.578us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	26.000s	1.138ms	200	200	100.00
		csrng_err	15.000s	49.165us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.015h	101.752ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1613	1630	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.29	98.35	96.11	99.07	96.70	91.77	100.00	97.14	90.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
  • Test csrng_stress_all_with_rand_reset has 8 failures.

    • 0.csrng_stress_all_with_rand_reset.69396662747424859210462075781126818012422326648077717075993785199854445261347
      Line 357, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6692507538 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6692507538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.csrng_stress_all_with_rand_reset.25385709858323152921754146715808614482885557608912371159059710744012661563604
      Line 384, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8024299214 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8024299214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 4 failures:
  • Test csrng_stress_all has 4 failures.

    • 11.csrng_stress_all.43156004534774317333712868790588917170541978496722567505654516511763352902196
      Line 323, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log

        UVM_ERROR @  35415013 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  35415013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.csrng_stress_all.14490908581918458815481022515056073075040159781393962483004206249265637786688
      Line 340, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log

        UVM_ERROR @ 1235115855 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 1235115855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 7.csrng_stress_all.77985487480316785795339436147193471034393586786690622474483288827805226212334
      Line 325, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all/latest/run.log

        UVM_ERROR @  15947639 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  15947639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.csrng_stress_all.68517672138622471896515035151728285151457630615291992233177076941371051382889
      Line 327, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_stress_all/latest/run.log

        UVM_ERROR @  51696432 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  51696432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
  • Test csrng_stress_all_with_rand_reset has 2 failures.

    • 8.csrng_stress_all_with_rand_reset.68944297636656625999448069383445923156165992047024118546771204538341471955783
      Line 292, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 487888937 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 487888937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.csrng_stress_all_with_rand_reset.79293152918187724207340259526467508989971762349235151647528242061105919307030
      Line 321, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12674690613 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12674690613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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