CSRNG Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	23.058us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	35.022us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	14.804us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	29.000s	527.337us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	17.000s	1.276ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	296.130us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	14.804us	20	20	100.00
		csrng_csr_aliasing	17.000s	1.276ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	20.000s	837.286us	200	200	100.00
V2	alerts	csrng_alert	56.000s	3.823ms	500	500	100.00
V2	err	csrng_err	13.000s	106.020us	500	500	100.00
V2	cmds	csrng_cmds	11.100m	62.326ms	50	50	100.00
V2	life cycle	csrng_cmds	11.100m	62.326ms	50	50	100.00
V2	stress_all	csrng_stress_all	32.800m	156.505ms	49	50	98.00
V2	intr_test	csrng_intr_test	8.000s	27.485us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	58.258us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	1.388ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	1.388ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	35.022us	5	5	100.00
		csrng_csr_rw	8.000s	14.804us	20	20	100.00
		csrng_csr_aliasing	17.000s	1.276ms	5	5	100.00
		csrng_same_csr_outstanding	13.000s	928.659us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	35.022us	5	5	100.00
		csrng_csr_rw	8.000s	14.804us	20	20	100.00
		csrng_csr_aliasing	17.000s	1.276ms	5	5	100.00
		csrng_same_csr_outstanding	13.000s	928.659us	20	20	100.00
V2		TOTAL			1439	1440	99.93
V2S	tl_intg_err	csrng_sec_cm	6.000s	68.919us	5	5	100.00
		csrng_tl_intg_err	21.000s	1.992ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	10.000s	47.380us	50	50	100.00
		csrng_csr_rw	8.000s	14.804us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	56.000s	3.823ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.800m	156.505ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	56.000s	3.823ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.800m	156.505ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	56.000s	3.823ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	21.000s	1.992ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
		csrng_sec_cm	6.000s	68.919us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	20.000s	837.286us	200	200	100.00
		csrng_err	13.000s	106.020us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	21.967m	99.078ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1619	1630	99.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.31	98.35	96.11	99.07	96.70	91.84	100.00	97.14	90.76

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test csrng_stress_all_with_rand_reset has 6 failures.
  - 1.csrng_stress_all_with_rand_reset.481697890035838193352202996283618220147268530602598261174617379304146274763
    Line 320, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49207742600 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 49207742600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.csrng_stress_all_with_rand_reset.43427314774080169209562388282718305888563567618700693847908896614177267075211
    Line 384, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16004339055 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16004339055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test csrng_stress_all_with_rand_reset has 4 failures.
  - 0.csrng_stress_all_with_rand_reset.35348658236080785031271046023761860090223189606485837264625795687977462760123
    Line 334, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16015348455 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 16015348455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.14283376972273381935467218457436027048847144831642150490772986355700533363009
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2914558207 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2914558207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 6.csrng_stress_all.40742677120174956113334717499039395977088693904415484642019203136404322339327
    Line 330, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1574931542 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1574931542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

CSRNG Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `07b417ef03`